طراحی مدارهای منطقی

1. طراحی مدارهای منطقی دانشگاه آزاد اسلامی واحد پرند نیمسال دوم 92-93

2. طراحی مدارهای منطقی دانشگاه آزاد اسلامی واحد پرند ICs (Mux, Decoder, ROM, PLA, PAL)

3. Where are we? • Far now  Basic logic design • More complex integrated circuits (ICs) • Integrated circuits • Small-Scale Integration (SSI) • Packages  typically contain one to four gates, six inverters, or one or two flip-flops • Medium-Scale Integration (MSI) • Like  adders, multiplexers, decoders, registers, and counters • Package  12 to 100 gates • Large-Scale Integration (LSI) • Package  100 to a few thousand gates • Very-Large-Scale Integration (VLSI) • Packge Several thousand gates or more

4. Contents • Multiplexer • Three-state buffer • Decoder, Encoder • ROM • PLD • PLA • PAL • CPLD • FPGA

5. Multiplexer (MUX) • Multiplexer • A group of data inputs • A group of control inputs • The control inputs are used to select one of the data inputs and connect it to the output terminal

6. Multiplexer (MUX) • Multiplexer

7. Multiplexer (MUX) • Multiplexer 4:1  With Mux 2:1 • Multiplexer 8:1  With Mux 2:1

8. Multiplexer (MUX) • Applications • Data selector =

9. Multiplexer (MUX) • Applications • Implement general logic functions

10. Multiplexer (MUX) • Multiplexer • High/low output • High/low enable

11. Three-State Buffer • Buffer • A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system. • A simple buffer may be used to increase the driving capability of a gate output

12. Three-State Buffer • Three-State Buffer = Tri-State Buffer • Normally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other • Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together • B open  High-impedance = Hi-Z

13. Three-State Buffer • Three-State Buffer = Tri-State Buffer

14. Three-State Buffer • Data selection

15. Three-State Buffer • 4-Bit Adder with Four Sources for One Operand • Integrated Circuit with Bi-Directional Input-Output Pin

16. Decoder/Encoder • Decoder  n to 2n • Generates all 2nminterms/maxterms of the three input variables • Exactly one of the output lines will be 1 for each combination of the values of the input variables

17. Decoder/Encoder • 4 to 10 Decoder

18. Decoder/Encoder • Example

19. Decoder/Encoder • Encoder  Reverse function of decoder • 8-to-3 Priority Encoder

20. ROM  Read-Only Memory • An array of semiconductor devices that are interconnected to store an array of binary data • Data can be read out whenever desired, but the stored data cannot be changed under normal operating conditions

21. ROM  Read-Only Memory • Typical  32× 4 , 512× 8

22. ROM  Read-Only Memory • One possible internal structure of 8× 4 ROM

23. ROM  Read-Only Memory • Example  Multiple-output combinatorial circuits

24. PLD  Programmable Logic Device • PLD  a general name for a digital integrated circuit • capable of being programmed to provide a variety of different logic functions • Changes in the design can easily be made by changing the programming of the PLD without having to change the wiring in the system

25. PLD  Programmable Logic Device • PLA  Programmable Logic Array • PLA with n inputs andm outputs can realize • m functions of n variables

26. PLD  Programmable Logic Device • PLA  Programmable Logic Array

27. PLD  Programmable Logic Device • PLA  Programmable Logic Array

28. PLD  Programmable Logic Device • PAL  Programmable Array Logic • Special case of PLA • AND array is programmable and the OR array is fixed • Less expensive than PLA • Easier to program

29. PLD  Programmable Logic Device • PAL  Programmable Array Logic • Example  Full-Adder

30. PLA vs. PAL vs. ROM • PLA/PAL  AND array • ROM  decoder • PLA/PAL  SOP • ROM  Truth table