Ethernet Bomber Stand-Alone / PCI-E controlled Ethernet Packet Generator

1. Ethernet BomberStand-Alone / PCI-E controlled Ethernet Packet Generator Characterization Presentation Oren Novitzky & Rony Setter Advisor: Mony Orbach Spring 2008 – Winter 2009

2. Contents • General description • Project goals • System description • Top level block diagram • HW and SW requirements • Project millstone

3. General Description • The demand for effective, real-time Ethernet monitoring and analysis devices requires a high-speed HW implemented Ethernet packet generator (“Bomber”).

4. Project Goals • Developing a hardware Ethernet packet generator and transmitter for Ethernet network and devices testing. • Support Stand-alone operation mode (PCI-E controlled – Optional). • Implementation of the system on Altera PCI-E Development kit board with Stratix II GX FPGA.

5. Project Goals • Learning common communication protocols such as Ethernet, UDP, IP • Learning HW development language (VHDL)

6. System Description optional PC Stand Alone operation mode: Generating and transmitting Ethernet packets. Configuration through Ethernet protocol as well. Configuration through PCI-E PCI-E Bomber Network Ethernet

7. Top Level Block Diagram FPGA Ethernet MAC Altera MegaFunc UDP/IP Packet generator PHY Marvell MII Payload Data base NIOSII Core RJ-45 PCI-E interface – 2.5 Gb/s Altera MegaFunc (optional) External Ethernet 10/100 Mbps Creating UDP/IP packets in Transport/Network layers . Implementation with NIOS II Core, using FPGA memory. External memory usage necessity is to be examined. Sending packets through Marvell Physical layer (board Hw) Using RJ-45 connector for twisted pair Creating Ethernet packets in Datalink layer Implementation with Altera Mega function Ethernet MAC Optional implementation of PCI-E interface for configuration purpose only.

8. HW & SW Tools SW: Quartus II – Altera Nios II – Altera SoPC Builder - Altera Megacore-IP library - Altera HDL-Designer HW: PCIe DevelopmentBoard - Altera

9. Project Milestones Week