2009 ITRS Emerging Research Devices Working Group Face – to – Face Meeting

1. 2009 ITRSEmerging Research DevicesWorking GroupFace – to – Face Meeting Jim Hutchby – Facilitating Dolce La Hulpe Brussels Hotel 135, Chaussée de Bruxelles, 1310 La Hulpe, BEL Room – Mahogany (Near) Brussels, Belgium Wednesday, March 18, 2009 8:00 a.m. – 5:30 p.m.

2. Emerging Research Devices Working Group • Rick Kiehl U. Minn • Suhwan Kim Seoul Nation U. • Hyoungjoon Kim Samsung • Atsuhiro Kinoshita Toshiba • Dae-Hong Ko Yonsei U. • Hiroshi Kotaki Sharp • Atsuhiro Kinoshita Toshiba • Franz Kreupl Qimonda • Nety Krishna AMAT • Zoran Krivokapic AMD • Phil Kuekes HP • Jong-Ho Lee Kyungpook Nation U. • Lou Lome IDA • Hiroshi Mizuta U. Southampton • Fumiyuki Nihei NEC • Ferdinand Peper NICT • Yaw Obeng NIST • Dave Roberts Air Products • Kaushal Singh AMAT • Sadas Shankar Intel • Atsushi Shiota JSR Micro • Satoshi Sugahara Tokyo Tech • Shin-ichi Takagi U. Tokyo • Ken Uchida Toshiba • Yasuo Wada Toyo U. • Rainer Waser RWTH A • Franz Widdershoven NXP • Jeff Welser NRI/IBM • Philip Wong Stanford U. • Kojiro Yagami Sony • David Yeh SRC/TI • In-Seok Yeo Samsung • In-K Yoo SAIT • Peter Zeitzoff Freescale • Yuegang Zhang LLLab • Victor Zhirnov SRC • Hiroyugi Akinaga AIST • Tetsuya Asai Hokkaido U. • Yuji Awano Fujitsu • George Bourianoff Intel • Michel Brillouet CEA/LETI • Joe Brewer U. Florida • John Carruthers PSU • Ralph Cavin SRC • An Chen AMD • U-In Chung Samsung • Byung Jin Cho KAIST • Sung Woong Chung Hynix • Luigi Colombo TI • Shamik Das Mitre • Erik DeBenedictis SNL • Simon Deleonibus LETI • Kristin De Meyer IMEC • Michael Frank AMD • Paul Franzon NCSU • Akira Fujiwara NTT • Christian Gamrat CEA • Mike Garner Intel • Dan Hammerstrom PSU • Wilfried Haensch IBM • Tsuyoshi Hasegawa NIMS • Shigenori Hayashi Matsushita • Dan Herr SRC • Toshiro Hiramoto U. Tokyo • Matsuo Hidaka ISTEK • Jim Hutchby SRC • Adrian Ionescu ETH • Kohei Itoh Keio U. • Kiyoshi Kawabata Renesas Tech • Seiichiro Kawamura Selete

3. Review Administrative Aspects Deliverables, Timeline, and Next Steps Proposed Chapter Outline and Page Count/Allocation Technology Entry Inclusion Criteria Broadly inclusive Maturity Metric (current publications) Review Major Decisions Hiramoto-san, U-In Chung, and Adrian Ionescu agree to serve as co-chairs of ERD with Jim Hutchby as chair. Guiding Principles – In the 3rd principle change “Novel Energy Transfer …” to “Novel Information Transfer…” Begin to merge Memory technologies with Storage technologies in 2010. Enter Carbon-based Nanoelectronics as a potential solution 2009 ITRS ERD Chapter Preparation Business Meeting Objectives (1/3)

4. Decide Structure & Major Technical Entries for Memory, Logic and Architecture Sections Factors considered Structure Content (particularly proposed numerical content) considering 1) Current experimental values, and 2) Long term potential values/goals for quantitative metrics Decide Technology entries (drop/add/move to Transition Table) Sections Logic Devices (including relevant materials issues w/ ref. to ERM) Memory Devices (including relevant materials issues w/ ref to ERM) Emerging Research Architectures (Decide approach for Architecture Section and build a strong connection between Logic & Architecture Sections). 2009 ITRS ERD Chapter Preparation Business Meeting Objectives (2/3)

5. Review/critique each Technology Entry Major barrier and/or weaknesses Requirement(s) for new materials Most important research questions to be addressed (materials and device structure) Level of risk and anticipated maturation time Decide Critical Assessment & Guiding Principle Sections Critical Assessment Memory Logic Guiding Principles – “Beyond CMOS” Discuss Proposal for Highlighting Promising Options for Emerging Memory Technologies 2009 ITRS ERD Chapter Preparation Business Meeting Objectives (3/3)

6. 7:30 Gathering time 8:00 Introductions 8:10 Review meeting objectives and agenda Hutchby 8:20 Review of Administrative Aspects Hutchby Deliverables, Timeline, Events, & Next Steps Chapter Outline, Page Count & Allocation Cross TWG Linkages & Meetings 8:30 Review/Discuss Status of Major Tech Sections Section outline Table structure (Row headers, etc.) Table Content (Current & projected tables) Key materials issues 8:30 Memory Devices Zhirnov 10:00 Break ITRS ERD WG Meeting – March 18, 2009Agenda

7. 10:15 Logic Devices Bourianoff 11:45 MASTAR Readiness for III-V & Ge MOSFETs Ng 12:00 Lunch 12:30 Emerging Research Materials Garner 1:30 Architectures Cavin 2:30 Discuss/Decide Difficult Challenges Hutchby 3:15 Discuss Evaluation & Guidance Sections 3:15 Critical Assessment Hutchby 3:45 Guiding Principles Hutchby 4:00 Discuss Proposal for Highlighting Promising Hutchby Options for Emerging Memory Technologies 4:45 Review ERD/ERM Beyond CMOS IRC Pres. All 5:25 Wrap up and Review Actions Required All 5:30 Adjourn ITRS ERD WG Meeting – March 18, 2009Agenda

8. Scope (1 page) Difficult Challenges (1) Taxonomy Chart (1) Devices Memory Devices (13) Logic Devices (15) Architectures (10) Critical Assessment (6) Fundamental Guiding Principles (3) Total Pages (50) Draft ERD Chapter Outline DRAFT

9. ERD Function Leader Chapter Chair – North America Hutchby Chapter Co-chair – Europe Ionescu Chapter Co-chair – Japan ERD Hiramoto Chapter Co-chair – Korea ERD Chung Memory Zhirnov Logic Bourianoff Architecture Cavin Editorial Team Hutchby, Bourianoff, Cavin, Chung, Garner/Herr, Hiramoto, Ionescu, Zhirnov ITRS Liaisons PIDS Ng, Hutchby FEP Colombo Modeling & Simulation Shankar/Das Materials Garner Metrology Herr/Obeng Design Yeh/Bourianoff More than Moore Brillouet Proposed 2009 ERD Working Group Organization New in 2009

10. ERD Chapter due August 21, 2009 Changed in San Francisco Major Tasks and Time Line Outlines for Memory, Logic, Architecture, Mat’l March 18 Technology Requirements Tables July 1 Guiding Principles Section March 18 Draft Text Completed Memory, Logic, Architecture, Material June 6 Functional Organization & Critical Review July 20 Scope, Difficult Challenges, etc. July 27 Chapter Completed August 21 Chapter Frozen Sept. 15 Major Face-to-Face Meetings in 2009 ITRS/ERD Meeting near Brussels, Belgium March 18 ITRS/ERD Meeting at Semicon West (SF, CA) July 12 ERD/ERM Meeting at IEDM in Washington Dec. 6 ITRS/ERD Meeting near Hsinchu, Taiwan Dec. 13 2009 ITRS/ERD Major Deliverables and Timeline

11. Decisions for 2009 Chapter • Memory • Include device structural aspects of the new NW PCRAM in ERD with a summary of the materials issues. Include more materials information in ERM on this topic. • Include the Spin Torque Transfer MRAM in ERD/ERM. • We will not include “Storage” technologies in 2009, but will begin to merge “Memory” and “Storage” technologies in 2010. At that time we will begin to include the “Magnetic Domain” or “Racetrack Memory” in ERD. • We will keep nanomechanical memory in ERD Memory Table. • Move the Ferroelectric Effects Tunneling Barrier Memory from the Electronic Effects Memory category to the Memory Transition Table • Leave “Redox type” memories in the ERD. These are different than ionic cation migration effects memory. • By categorizing using a physics-based system, a given material that exhibits 2 or more effects will be listed in each category. • Drop the Charge Trapping Memory as a Technology Entry – move to Transition Table? • Drop the Capacitive Memory Table

12. Decisions for 2009 Chapter • Logic • We will have 3 Logic tables in 2009. They will be titled: • Table 1: “MOSFET: Extending the Channel of MOSFETs to the End of the Roadmap” • Table 2: “Non-Conventional FET, Charge-based Extended CMOS Devices” • Table 3: “Non-FET, Non Charge-based ‘Beyond CMOS’ Devices” • ERD/ERM recommends carbon-based nanoelectronics to include CNT, graphene for more resources and roadmapping for IRC as part of promising technologies for 5-10 years demonstration horizon • Carbon-based nanoelectronics will be included in the 2009 ERD chapter via a two new Potential Solutions tables – for materials and for device issues. • Seven potential technologies were considered: • Carbon-based Nanoelectronics • Collective spin • Spin torque transfer • Atomic and electrochemical metal • CMOL/FPNI • Single Electron Transistor • NEMS

13. Action Items (1/3)

14. Action Items (2/3)

15. Action Items (3/3)

16. Backup Slides

17. 2009 ITRSEmerging Research DevicesEditorial – Driver Team MeetingCharter and Scope George Bourianoff Mike Garner Jim Hutchby Victor Zhirnov Santa Clara, CA October 13, 2004 Edited December 10, 2006

18. On behalf of the 2009 ITRS, develop an Emerging Research Devices chapter to -- Critically assess new approaches to Information Processing technology beyond ultimate CMOS Identify most promising approach(es) to Information Processing technology to be implemented by 2024 To offer substantive guidance to – Global research community Relevant government agencies Technology managers Suppliers Charter of ERD Chapter

19. Integrated emerging research memory, logic and new architecture technologies enabled by supporting -- Materials and process technologies Modeling and simulation Metrologies Selection of specific technical approaches shall be Guided by fundamental requirements Bounded by ERD’s topic selection criteria Scope of ERD Chapter

20. Devices and Architectures – Published by 2 or more groups in archival literature and peer reviewed conferences, or Published extensively by 1 group in archival literature and peer reviewed conferences Technology Entry (by itself or integrated with CMOS) must address a major electronics market. Materials and Fabrication Technologies – Materials and processes that address the specific material needs defined by emerging research device technology entries Supporting disciplines – specify for crosscut TWGs Metrologies Modeling & simulation Scope of ERD ChapterCriteria for Including Technology Entries

21. Conventional Scaled CMOS Architecture Linear Cellular arrays Reconfigurable Quantum Boolean Data Representation Analog Phase state Quantum qubit Digital New Information Process Technologies Device Spintronics Quantum CNT FETs Molecular Scaled CMOS Ferromagnetic Material Complex metal oxides Carbon NTs Silicon Macro molecules Nanowires State Variable Molecular state Spin orientation Electric charge Phase state Bio inspired A Taxonomy for Nano Information Processing Technologies

22. ERD ITWGEmerging Research DevicesWorking GroupProposal for Assessing Technology Options for Emerging Research Memory Devices Jim Hutchby & Mike Garner Friday March 20, 2009

23. ERD/ERM is seeking IRC guidance on whether we should conduct a review and assessment of emerging research memory technologies with the goal of recommending those most promising for detailed roadmapping and accelerated research. Assess technology capability of being scaled beyond the 15nm node. Identify precompetitive research required for top candidates to scale beyond the 15nm node Process will be completed in April 2010 with an oral report to the IRC in the Spring ITRS Meeting followed by a written report/recommendation to the IRC. Objective of IRC/ERD/ERM discussion of this request from Samsung, Hynix, and Micron

24. Samsung, Hynix , and Micron proposed that the ERD/ERM identify memory technologies needing more focused support Proposal: ERD & ERM hold a workshop in April 2010 to review and assess emerging research memory devices Goal: Identify emerging research memory technologies that merit more detailed roadmapping and more focused research. Process: Same Process as the Logic Assessment in 2008 Champions present Pros, Cons and research needed for technology Friendly critic presents balanced assessment White paper prepared on each memory and circulated prior to the meeting Face to Face Presentations & Discussion Voting on Promising Technology Identify Critical Research Needed Assessment of Promising Emerging Memory Devices

25. Straw Candidate Emerging Research Memory Technologies • Capacitive Memory • FeFET Memory • Resistive Memory • Nanoelectromechanical • STT MRAM • Thermal PCM • FUSE/Anti-FUSE • Nanowire PCM • Electrochemical Memory • Cation migration • Anion migration • Electronic Effects Memory • Charge trapping • Mott Transition • FE barrier effects • Macromolecular Memory • Molecular Memory

26. DRAFT GOAL With the goal of providing input to resource allocation decisions, ERD/ERM WGs will conduct an in-depth review and assessment of specific emerging research memory devices to highlight the most promising device technologies for detailed roadmapping and acceleration of pre-competitive*research and development. (*Pre-competitive refers to those technologies capable of being scaled beyond the 15nm node.)

27. DRAFT SCOPE The scope of the review of emerging research memory technologies will assess scalability beyond the 15nm node. • Identify precompetitive research needed to enable scaling beyond the 15nm node. • Assessment will encompass both stand-alone and, where different, embedded emerging research memory technologies.

28. Draft Timetable

29. Develop/decide process, milestones, timeline Develop invitation to advocates & opponents Introduction Potential of technology – fundamental limits Barriers – Fundamental vs. technological/engineering Evaluation Criteria / Benchmark memory technology Definition of maturing, high potential specific devices for roadmapping Readiness in ~ 5 - 10 years Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

30. Identify Major emerging research memory technology candidates Strong technical proponent and opponent teams and their leaders Knowledgeable ERD/ERM mentor for each proponent team Key questions to be addressed by the teams Background materials for each technical candidate Issue invitations to team leaders and obtain their commitments Obtain a white paper & background materials from each candidate technology proponent team for ERD/ERM review Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

31. REDO THIS SLIDE

33. Conduct a FxF review of categories with each proponent & friendly critic team making a presentation On second day of ERD/ERM FxF meeting, discuss/decide ERD/ERM’s recommendation of most promising emerging research memory technology options. Mentors will lead the discussion of their candidate technology Write & submit report to the IRC on ERD/ERM WG’s recommendations Proposed ERD/ERM WG Process for Assessing Candidate Emerging Research Memory Device Technology Options

34. Decision Making & Majority Voting Scheme Each member of ERD WG will be given a maximum of X votes to use in voting for their top X choices among the candidate technologies (Majority Voting scheme) ERD/ERM WG members present in the FIRST DAY Workshop & the SECOND DAY meeting will be eligible to vote at SECOND DAY meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation, Only 0 or 1 vote can be cast for any candidate technology Member does not have to use all X votes, but cannot use more than X votes. All members can participate in the straw vote. The Candidate Technologies will be ordered according to which received the largest number of votes. Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus. REDO THIS SLIDE

35. 9:20 Review Process for selecting beyond CMOS emerging technologies 9:45 Discuss Technologies 9:45 NEMS Switch Technology 10:05 Spin Torque Transfer Technology 10:25 Carbon-based Nanoelectronics 10:45 Break 11:00 Atomic Switch / Electrochemical Metal Switch 11:20 Collective Spin Devices (including M-QCA) 11:40 Single Electron Transistors 12:00 CMOL and FPNI ERD “Beyond CMOS” Technology Selection MtgAgenda – SECOND DAY REDO THIS SLIDE

36. 12:50 Preliminary vote on technologies – Majority voting process 1:00 Discuss preliminary results 1:45 Second vote on technologies 2:00 Discuss the leading technologies resulting from vote 2:30 Final vote on the leading technology(ies) to determine if we have approximate consensus (75% of those voting) to recommend one or more for roadmapping and enhanced engineering development 2:45 Decide next steps in roadmapping the chosen technologies ERD “Beyond CMOS” Technology Selection Mtg Agenda – SECOND DAY (Cont’d) REDO THIS SLIDE

37. Decision Making & Majority Voting Scheme Each member of ERD WG will be given a maximum of 3 votes to use in voting for their top 3 choices among the candidate technologies (Majority Voting scheme) ERD/ERM WG members present in the July 11 Workshop & the July 12 FxF meeting will be eligible to vote at July 12 meeting, based on their personal technical judgment, independent of their corporate affiliation or regional representation, Only 0 or 1 vote can be cast for any candidate technology Member does not have to use all 3 votes, but cannot use more than 3 votes. All members can participate in the straw vote. The Candidate Technologies will be ordered according to which received the largest number of votes. Consensus approval will be our goal, but a 75% affirmative vote will be required as a minimum. This is what is meant by the term approximate consensus.