1 / 24

Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis

Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis. DSP 'Swiss Army Knife'. April 20, 2005. Overall Project Objective: General Purpose Digital Signal Processing Chip. MILESTONE 13 Short Final Presentation. Project Description.

blenda
Download Presentation

Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis DSP 'Swiss Army Knife' April 20, 2005 Overall Project Objective: General Purpose Digital Signal Processing Chip MILESTONE 13 Short Final Presentation

  2. Project Description • We aimed to implement a “general discrete-signal network that appears, in various forms, inside many digital signal processing (DSP) applications.”[1] • Specifically, the circuit is a ‘comb’ filter followed by a second-order recursive network (referred to henceforth as a ‘biquad’).

  3. Project Description (Huh?) • What does that mean? • ‘Comb’ = selective additive delay • ‘Biquad’ = Feedback loop with multiply and adds. • Overall effect is to implement 22 distinct functions based on the input coefficients.

  4. Marketing • Motivation

  5. Marketing –System Integration • How Does Our Circuit Fit Into the Bigger Picture? • Focus on Audio/Video Applications • Audio: • Digital Radios / MP3 Players (i.e. Motorola, Lucent, Texas Instruments) • Digital Music Synthesis / Sampling (i.e. Yamaha, Korg) • Noise Reduction (i.e. Dolby) • Video: • Comb Filter to separate color and brightness (i.e. Sony, Toshiba) • Others: • Motor Control Functions such as RPM (i.e. Ford, GE)

  6. Design Process • How did you get from description to actual implementation?

  7. Behavioral/AlgorithmicDescription • How exactly does it work?

  8. Dataflow • Example of function 1 of 22: The Moving Averager • Our circuit implements a simple moving average over 8 or 16 data points. • An average is simply the sum of a data set divided by the number of data points. The moving average takes a set number of data points to be used and as new data comes in, old data "falls off" the end of the calculation. For example…

  9. Dataflow A Moving Averager Smoothes a Signal to Reduce Noise

  10. Dataflow A moving average over 8 data points: 1.0 1.125 1.375 2.25 3.0 3.0 3.625 4.75 4.125 4.75 4.625 4.25 0 4 1 6 3 9 5 0 6 7 2 1 8

  11. Emulations – C Code

  12. Emulations - Soft-IP Top Level Verilog Verified Complex Function

  13. Floorplan Evolution

  14. Road to Verification – fp_mult verilog vs. schematic VSIM 1> run # x xxxxxx xxxxx * x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 * 0 000000 00000 = 0 000000 00000 # 0 011110 00000 * 1 011101 11000 = 1 011100 11000 # 0 100001 00100 * 0 100000 01000 = 0 100010 01101 # 0 100001 01110 * 0 100000 00001 = 0 100010 01111 # 0 100001 11100 * 0 100000 11110 = 0 100011 11010 # 0 100100 11110 * 0 100010 11000 = 0 101000 10110 # 1 100100 11110 * 1 100010 11000 = 0 101000 10110 # 0 100001 00010 * 0 100001 11110 = 0 100100 00000 # ** Note: $finish : fp_mult_tb0.v(41) # Time: 9 ns Iteration: 0 Instance: /tester

  15. Road to Verification – fp_add verilog vs. schematic • VSIM 1> # x xxxxxx xxxxx + x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 + 0 000000 00000 = 0 000000 00000 # 0 011110 00000 + 1 011101 11000 = 0 011011 00000 # 0 100001 00100 + 0 100000 01000 = 0 100001 11000 # 0 100001 01110 + 0 100000 00001 = 0 100001 11110 # 0 100001 11100 + 0 100000 11110 = 0 100010 01101 # 0 100100 11110 + 0 100010 11000 = 0 100101 00110 # 1 100100 11110 + 1 100010 11000 = 1 100101 00110 # 0 100001 00010 + 0 100001 11110 = 0 100010 10000 # ** Note: $finish : fp_add_tb0.v(40) # Time: 9 ns Iteration: 0 Instance: /tester

  16. Road to Verification – Top Level Structural • Verified all of the functions for the ‘Swiss Army Knife’ in Schematic. • Plotted outputs using custom made code & MatLab. • From plots it is evident that the accuracy is excellent.

  17. Issues Encountered

  18. Issues Encountered • Misunderstanding of DSP terms and main blocks represented in IEEE paper. • Booth encoding was time consuming and problematic. • Imaginary numbers proved less of a difficulty than we initially thought. • Issues correctly identifying the source of errors in analog simulation.

  19. Specs • Pin Specs • Inputs (76 pins) • X[n] : 12 pins • a1, a2, b0, b1, b2: 5 * 12 = 60 pins • vdd, gnd, N, c1 : 4 * 1 = 4 pins • Outputs (12 pins) • Y[n] : 12 pins • TOTAL: 88 pins

  20. Specs • Part Specs • Fp_add: • Transistors: 2,274 • Area: 103.5450μm x 124.200μm = 12,860.29μm2 • Density: 0.18 • Fp_mult: • Transistors: 2,464 • Area: 95.5450μm x 141.750μm = 13,543.50μm2 • Density: 0.18 • Comb: • Transistors: 6,290 • Area: 99.360μm x 151.290μm = 15,032.17μm2 • Density: 0.42

  21. Specs • Chip Specs • Transistors: 34,564 • Area: 434.520μm x 395.460μm = 171,835.28μm2 • Density 0.20

  22. Layout • Layer Masks • Full chip layout

  23. Layout - Overlay

  24. Conclusions • Jake • Layout? • Nick • Layout / Sims? • Darren • Verilog / Matlab / C / DSP? • Craig • Verilog / schematic / layout?

More Related