Presented By Yuanzhong Wan Instructor: Professor Maitham Shams Dept. of Electronics

1. Trends in Low-Power RAM Circuit TechnologiesAUTHOR: KIYOO ITOH, KATSURO SASAKIPROCEEDINGS OF IEEE, NO.4 APRIL 1995 Presented By Yuanzhong Wan Instructor: Professor Maitham Shams Dept. of Electronics Carleton University March, 2002 Prepared by Yuanzhong Wan

2. Contents 1. Introduction 2. Sources of power dissipation 3. Low power DRAM circuit • Active power reduction • Data retention power reduction • Prospective 4. Low power SRAM circuit • Active power reduction • Data retention power reduction • Prospective Prepared by Yuanzhong Wan

3. Introduction • Low power CMOS RAM • Reduced charging capacitance • Reduced operating voltage • Reduced static current • Low operating voltage & high speed • => threshold voltage (VT) scaling • VT => subthreshold dc current => active and retention current  Prepared by Yuanzhong Wan

4. Source of Power Dissipation Prepared by Yuanzhong Wan

5. Sources of power dissipation • Power source memory cell array, decoders(row & column), periphery • Active power P = VDD*IDDn+m=2 IDD = m*iact+ m*(n-1)*ihld + (n+m)*CDE *VINT* f + CPT*VINT*f +IDCP (for read cycle)VDD: external supply voltage, IDD : current of VDDihld:effective data retention current of inactive cell CDE: output node cap. of each decoder iact: effective current of active cell VINT:internal supply voltage IDCP: tatal static(DC) current of periphery CPT : total cap. of CMOS logic and driving circuits in periphery, f: operating freq. (=1/tRC ) Prepared by Yuanzhong Wan

6. The Active Power of DRAM Prepared by Yuanzhong Wan

7. Active Power : DRAM • Destructive readout • needs amplification and restoration • data line is charged and discharged with a large voltage swing of VD& charge current of CDVD f • IDD [m CD *VD +CPT*VINT] *f + IDCP (CD : data line capacitance) • Reducing active power • Reducing charging capacitance (m CD , CPT) • Lowering external & internal voltages(VD , VINT , VD) • Reducing static current (IDCP) • m *CD *VD must be reduced while maintaining acceptable SNR Prepared by Yuanzhong Wan

8. Active Power : SRAM Prepared by Yuanzhong Wan

9. Active Power : SRAM • Non-destructive readout • never require restoration of cell data • IDD [m* iDCt +CPT*VINT] *f + IDCP • Reduce active power • static current => dominates the total active current • voltage, capacitance • SNR issue is not so serious due to ratio operation Prepared by Yuanzhong Wan

10. Data Retention Power Sources • DRAM • In data retention mode, memory chip has no access from outside & data are retained by refresh operation • Refresh operation : reading data and restoring • IDD [m *CD *VD +CPT*VINT] *(n/tREF) + IDCP • IDCP becomes relatively large for ac current components because of small n/tREF • SRAM • static cell leakage current m*n*ihld is the major source Prepared by Yuanzhong Wan

11. Low Power DRAM • Active power reduction • Charging capacitance reduction • Partial activation of multi-divided data-line / word-line • Refresh time increase • Operating voltage reduction • Half-VDD data line precharge • On-chip voltage down conversion • Signal-to-noise ratio improvement • DC current reduction • Data retention power reduction • Voltage reduction scheme • Refresh time extension Prepared by Yuanzhong Wan

12. DRAM : Active power reduction (1) 1) Charging capacitance reduction • Partial activation of Multi-divided data line • increasing number of cells causes an increased CD=> divide one data line into several sections • Shared I/O : further divides a multi-divided data line into two • Shared SA : provides doubled cell signal with halves CD • Shared Y decoder Prepared by Yuanzhong Wan

13. Multi-divided data line with shared I/O, SA, Y Decoder Prepared by Yuanzhong Wan

14. DRAM : Active power reduction (2) • Partial activation of multi-divided word line • Increase refresh time • Reduction of m is achieved with increasing the maximum refresh time of the cell, tREFmax • Refresh busy rate γ=tRCmin / (tREFmax / n) = (M/m) / (tRCmin/tREFmax) Prepared by Yuanzhong Wan

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16. DRAM : Active power reduction (3) 2) Operating voltage reduction • Half-VDD data line precharge Halves data-line voltage swing 3) DC current reduction • Pulse-operation technique Prepared by Yuanzhong Wan

17. Half-Vdd data-line precharge Prepared by Yuanzhong Wan

18. Pulse-operation technique Prepared by Yuanzhong Wan

19. DRAM : Data Retention Power Reduction • DC current reduction • minimizing on-chip voltage converters • (VDC,voltage up converter, substrate back-bias generator, VREF generator, half-VDD generator) • AC current reduction • Extending refresh time • Reducing refresh charge Prepared by Yuanzhong Wan

20. DRAM : Perspective • VT scaling is major concern => reduction of subthreshold current 1) CMOS basic circuit • Switched-power supply inverter with level holding • Switched-source impedance Prepared by Yuanzhong Wan

21. Switched Source Impedance Switched-power supply inverter with level holding Prepared by Yuanzhong Wan

22. DRAM : Perspective 2) Iterative Circuit Blocks • Subthreshold current reduction • Partial activation of Multi-divided power line Prepared by Yuanzhong Wan

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24. Partial activation of Multi-divided power line Prepared by Yuanzhong Wan

25. DRAM : Perspective 3) Memory cell • subthreshold current flows from the cell storage node to the data line while data line is held at the low level • Source-gate back-biasing scheme Boosted Sense ground Scheme Prepared by Yuanzhong Wan

26. SRAM : Active Power Reduction • DC current reduction • Partial Activation of Multi-divided word line • Pulse operation of word line circuitry Prepared by Yuanzhong Wan

27. Pulse Operation of Word Line Prepared by Yuanzhong Wan

28. Prepared by Yuanzhong Wan 3/3/02 Prepared by Yuanzhong Wan 28

29. SRAM : Perspective • Low-voltage operation capability is critical issue. • For high-speed operation , low VT designs are indispensable Prepared by Yuanzhong Wan

30. Conclusion • Low power CMOS RAM • Reduced charging capacitance • Reduced operating voltage • Reduced static current • Low power DRAM • partial activation of multi-divided data-line & word-line • Operating voltage reduction by half-VDD precharging, VDC and high SNR • Low power SRAM • Partially activating a multi-divided word line • Pulsing the word driver/column circuit • Prespective in Low power CMOS RAM design • Subthreshold current reduction circuit such as source-gate back-biasing in cell and iterative circuit block Prepared by Yuanzhong Wan

31. Reference • Kiyoo Itoh, Katsuro Sasaki, “Trends in Low-Power RAM Circuit Technologies”, PROCEEDINGS OF IEEE, NO.4 APRIL 1995 • Kiyoo Itoh, “VLSI Memory Chip Design”, Springer, 2001 • Brent Keeth, R. Jacob Baker, “DRAM Circuit Design, A Tutorial”, IEEE PRESS, 2000 Prepared by Yuanzhong Wan