Salt Chip For The UT Digital Data Processing Block & Serializer Requirements

1. Salt Chip For The UT Digital Data Processing Block& Serializer Requirements JC Wang June 6, 2013

2. Outline • Data processing: • UT common mode suppression algorithm. • Number of ADC bits in zero suppressed signal. • Serializer block: • Event packet format at the front end ASIC. • Data rates, number of e-ports/e-links for different event output options. • ASIC data buffer size. • Addendum • Reminder of low voltage routing and LDO on chip.

3. UT Data Processing • UT channel pedestal will be obtained offline from designated runs. Pedestal follower in SALT chip is not needed. • Noisy or bad channels will be masked out. • Common mode suppression is done on pedestal subtracted data. However, we should have the option to switch it off. • Linear common mode noise suppression does not apply to UT. • UT uses single threshold, comparing to 2 for VELO. Thresholds may be different for different channels. • Zero suppression is applied, but clustering is not needed. • ADC values will be truncated to reduce data size. • Pedestal, threshold, kill mask & CMS parameters etc are uploaded to front end ASICs during initialization.

4. UT Common Mode Suppression • Signal data are pedestal subtracted. • At the 1st stage, CM is calculated with a coarse rejection of real signals and special effects due to large signals in previous events. Please note that the selection window is not symmetric. • At the 2nd stage, selection channels in a small symmetric window. It would be better to repeat this step (3rd stage). • The number of channels used in the last stage CM calculation (N3), and the number of signal channels recovered (Nrec) if CM suppression is applied are counted. • If N3 is too small or Nrec is too large, it is better not to have CM correction. • Possible default parameter values: th1, th2, th3, thr= 5,ncm= 64, nrec= 31. • Parameters to output in NZS mode: NumChanCM = N3, NumChanSignal = Nsig, NumChanRecover = Nrec, CMValue = CM

5. ADC Precision After ZS • SALT chip has 6-bit ADC. After pedestal subtraction, it is equivalent to 5-bit for signals. • As there is very little charge sharing between adjacent strips even 5-bit may be overkill. • Currently we think that 3-bit may be enough. The 5-bit ADC values can be truncated into 3-bit after ZS. • This need to be justified in simulation with better electronics modeling. • We can compare track momentum resolution and ghost rate for 5-bit & 3-bit with dynamic range properly optimized. • For better electronics simulation we will include: • Strip capacitances and corresponding noise. • Coupling between adjacent strips, maybe also routing traces. • SALT channel noise. • SALT time curve. • Threshold uniformity. • …

6. UT Signal Data Flow Hybrid DCB DCB AMC40 Substrate ASICs AMC40 AMC40 Sensor Low mass data cable Cooling & support UT hybrid Data concentrator boards • Front end ASICs are on sensor hybrid. Signals from silicon strips are digitized, and processed. • Event packet is formed and saved in memory buffer. • Digital data are then sent from ASIC e-ports via e-links in data cable to data concentrator boards (DCB). • AMC40’s collect data from DCB via optical fiber, process data and send to DAQ machines. DCB DCB

7. UT Data Format (ZS) • Each hit data contains 7-bit channel ID & 3-bit ADC value. Chip ID etc are not needed. • At the beginning of event packet a 4-bit bunch crossing ID (BCID) is used to tag event. • One-bit PacketType follows to indicate if it is a normal packet (0) or a special one (1). • For an event (NumHits63) a normal packet is created. All hits are saved following a 6-bit Length = NumHits. • In an event (NumHits>63) individual hits are difficult to be used in reconstruction. A special packet is created including 8-bit NumHits and packet flag bits (001b). No individual hit is saved.Probability ~6x10-4 for the busiest chip. • Should the buffer be full. We need to truncate the event too. In this case the flag is (010b). • Sometimes there are not enough data to be sent out. We can fill it with dummy event packet with flat (100b) and BCID fixed to 1111b, NumHits to 11111111b. • We can have other special packet for other needs with different PacketFlag. size = 11 + NumHits*10 bits size = 16

8. UT Data Format (NZS) • In pedestal/noise runs or special test runs UT can be in non-zero-suppression (NZS) mode. • All 6-bit ADC values are sent out in sequential order, thus no channel ID is needed. • We also want to save parameters in digital process for debugging purpose (the number of parameters may increase when digital process is finalized): • Number of channels used in MCMS calculation. • Number of final signal channels (ADC > threshold). • Number of signal channels recovered by CMS. • Common mode from calculation, MSB for sign: positive(0), negative (1). • The event data size is fixed (4 + 4x8+128x6 = 804 bits).

9. UT Hits In Minimum Bias Events Min. bias events s = 14 TeV L = 2x1033 cm-2s-1 2400 beam-beam xing nu = 7.6 Region 0 One module • Every event only ~16% of chips have real hits. For the busiest chips, the probability ~70%. • For these chips/events we still need to send out information indicating that they have 0 hits. • Some chips/event can have >50% channels lit. We can save the only the number of hits, not individual hits. • The largest probability fora chip is ~ 6x10-4.

10. Number of Hits In Minimum Bias Events Min. bias events s = 14 TeV L = 2x1033 cm-2s-1 2400 beam-beam xing nu = 7.6 Region 0 One module • Number of UT clusters = 916, average cluster size ~1.6 with the current electronics parameters. • Of all 4192 ASICs, the average number of strips per chip per event ~ 0.35. For the busiest ones ~2.2 (~1.7% occupancy). • The inner radius of sensitive detection is 34 mm. • For the busy module, ~34 strip hits per event need to be read out from each end.

11. Data Rate Per Front End ASIC 3 x 320 Mbps e-links 2 x 320 Mbps e-links 1 x 320 Mbps e-links • In one scenario we record only beam-beam crossing events (2400/3564), and ignore beam-gas & non-beam events (1164/3564). • The data rate of most chips is between 320 – 640 Mbps. For the busiest one the data rate ~890 Mbps, which needs  3 active 320 Mbps e-links to transfer data. • Total data rate for the UT system ~1630 Gbps. The number of e-links ~8200.

12. Scenario That All Events Are Recorded 3 x 320 Mbps e-links 2 x 320 Mbps e-links 1 x 320 Mbps e-links • Record all bunch crossing events  Less economic but simpler • The highest data rate per chip =1034 Mbps. Four active e-links is needed. We want a spare e-port, this means that each ASIC needs total 5 e-ports in design. • The overall data rate ~2233 Gbps (37% increase from 1630 Gbps). • The total number of e-links ~8850 (8% increase from ~8200).

13. More on Event Output Options • AMC40 requires that the front end electronics send events of all bunch crossing (3564), not just beam-beam crossing (2400). One reason is that the BCID may not be long enough to solve ambiguity etc. • If we send only beam-beam events from ASIC to data concentrator board (DCB), we can generate dummy event packets for the rest at DCB. This, however, introduces further complication in DCB as event data are not aligned with 8-bit boundary. Thus insert a packet is non-trivial. • If we choose to send all events between ASIC and DCB the penalties are: more e-ports in ASIC, more data lines in module data cable, etc. • Another possibility is to increase the length of BCID and send out only beam-beam events from ASIC to BCD & to AMC40. As an estimation if BCID length = 9.3 (1164 / 2400 * 11 = 5.3) this option has the same data rate as that we save all events. So if BCID length =9 is acceptable we already gain.

14. Test of Buffer Size Needs • The sequence of UT signal processing is: ADC  PedSub CMS  ZS  Event packet  Memory buffer  Serialization  E-port & e-link  … • For UT what matters to de-randomizer is the buffer size, instead of event depth. • We choose the busiest chip to gain some ideas. The data rate is 890 Mbps when only beam-beam events are saved. It needs 3 e-links. • Other chips with less active e-ports may need bigger buffer if there is less room of its e-link capacity. But this can always be adjusted with number of active e-ports. <N> = 2.22 prob(N>63) = 2.4x10-4 Data rate: 890 Mbps for beambeam event only. Num of e-links = 3

15. Buffer Size and Buffer Overflow Rate • At each beam-beam bunch crossing data packet is formed and added into buffer (size=11+10*Nhit, or 16 for truncation). • If there is not enough space left, special overflow packet (16-bit) is saved. • At each bunch crossing (40 MHz), 3x8=24 bits are sent out. In case that saved data in buffer is less than 24, dummy packets (16-bit) are added. • Buffer size of 4 Kb may be reasonable ( overflow rate ~3x10-8). No buffer size limit Busiest chip

16. Summary • UT requires pedestal subtraction, optional CM suppression, & single threshold ZS in SALT chip. No linear CM is needed. • Currently UT truncates signal height value from 5 bits to 3 bits. This will be justified soon in simulation with better electronics model. • UT data packet format is proposed. Comments and suggestions will be taken in next revision. • Based on full simulation of an improved UT detector, 2400 beam-beam crossing bunch structure & L = 2x1033 cm-2s-1 we estimate data rate from each individual chip and number of e-ports needed. If only beam-beam events are saved, the busiest chips has 890 Mbps data and needs 3 active e-ports. If all events are saved it has 1033 Mbps data and needs 4 active e-ports. One spare e-port in design is suggested. • For the same chip, we estimate that it needs 4 Kb buffer memory. • The total number of e-links is 8200-8850, requiring ~ 600-700 DCBs. • Each UT module data cable needs ~ 200-240 data lines. If we have a lot lines the design becomes more complex.

17. Extra Slides

18. LV Power Supply Connection DC-DC converter Maraton Power supply Patch panel Low mass power cable • A Weiner Maraton power system is located in the counting room and/or in the cavern. It provides higher low voltage power. • The power is distributed via patch panels in the carven near the UT detector. • It is converted to proper voltage by DC-DC converters at the ends of the UT modules before sent to the front end ASICs via low mass power cables. • The ASICs have build-in LDO regulators. UT sensor hybrid Low mass data cable ASICs

19. New UT Configuration ½ pitch ½ length Most Sensors 512 vertical strips length ~10 cm pitch ~178 mm ½ pitch UTaX AAAAAABCDBAAAAAA Readout from top 2 2 2 2 2 2 4 4 4 2 2 4 2 2 2 2 readout from bottom • All modules are full module. • Readout from top & bottom are balanced. Region 0 6/7 modules 84/98 sectors Region 1 4 modules 80 sectors Region 2 6/7 modules 84/98 sectors

20. E-link and Data Concentrator Board 80/160/320 Mbps / Link Multiple links possible From https://espace.cern.ch/GBT-Project 3.2 Gbps GBTX width option of 112 instead of 80 increases bandwidth to 4.48 Gbps. Thus it may be able to support 14 e-links @ 320 Mbps. Send out data In unit of 8 bits Data concentrator board

21. E-links Per Module End and Data Lines s = 14 TeV L = 2x1033 cm-2s-1 2400 beam-beam xing • Data are collected by data concentrator boards (DCB) at both ends of the UT modules (EoM) via 320 Mbps e-links. • Data from multiple e-links are further packed according to GBTx and sent to AMC40 via optical fibers. • If only beam-beam events are saved, one EoM needs to support ~50 e-links, max = 92. If all events are saved, the value is ~60, max=113. • There are 3 SLVS signals between e-ports: clk, data_in, data_out. • Between ASIC & DCB the event data transfer is unidirectional. And clocks can be shared. • All e-link data lines to one EoM is via the same Kapton flex data cable. It needs about 2x92 to 2x113 connections plus clock and slow control lines. beam-beam events All events