Effective Assertion Techniques for Digital Systems Verification

1. Could be applied in checking properties... Formal verification: assertions Digitaalsüsteemide verifitseerimise kursus

2. … but also during simulation Simulation-based verification: assertions Digitaalsüsteemide verifitseerimise kursus

3. Assertion • Set of expressions that check the validity of certain conditions for variables over a period of time • If a condition is violated then an error message will be displayed that will report the location of the error • Assertions could be used during simulation or in checking properties formally Digitaalsüsteemide verifitseerimise kursus

4. Assertion • Allows observing internal signals: • Before they propagate to outputs • Can observe errors before they propagate to primary outputs • Applied in HW and SW debugging for long • Only recently standardized Digitaalsüsteemide verifitseerimise kursus

5. How to create assertions Two opposite strategies: • Find from spec properties that should hold in the implementation (liveness) • Find from spec properties that should not occur in the implementation (safety) + fairness properties Digitaalsüsteemide verifitseerimise kursus

6. Combinational and Sequential Assertions • Assertions not depending on time - combinational: N. (A != 0 ) && ( A & (A-1)) • Assertions depending on previous (following) clock cycles - sequential: N. (A-1 != A) -> (A == A+1) • The interwal between the 1st and last clock-cycles: time-window Digitaalsüsteemide verifitseerimise kursus

7. Hierarchy of assertions • As specs can be represented at different abstraction levels so can assertions: • Behavioral level • RTL • Logic level • etc... Digitaalsüsteemide verifitseerimise kursus

8. Assertion components • Assertion consists of 4 components: • Activating condition • Signalregister • Assertion statement • Reaction Digitaalsüsteemide verifitseerimise kursus

9. Assertion components Digitaalsüsteemide verifitseerimise kursus

10. Sequential assertions • Cyclic list: Digitaalsüsteemide verifitseerimise kursus

11. Assertions on signal change pattern Digitaalsüsteemide verifitseerimise kursus

12. More assertions • Check if a signal changed within a time-window • Check causality (change of one signal causes change in another) within a time-window Digitaalsüsteemide verifitseerimise kursus

13. Container Assertions • Check correctness after additional processing Digitaalsüsteemide verifitseerimise kursus

14. SystemVerilog Assertions • Although any HDL (VHDL, Verilog, etc.) will do, it may need a lot of coding … • …and the assertions can not be reused. • SystemVerilog (IEEE std 1364) offers standard assertions Digitaalsüsteemide verifitseerimise kursus

15. SystemVerilog Assertions • Two types of assertions in SVA: • Procedural assertions • Declarative assertions Digitaalsüsteemide verifitseerimise kursus

16. SVA: procedural assertions • Written to the code to be simulated – applied in simulation-based verification. • Example: assert (WR == 1'b1 && CS == 1'b0) $display ("INFO: memory ready"); // pass clause else $display ("ERROR: cannot write"); // fail clause Digitaalsüsteemide verifitseerimise kursus

17. SVA: declarative assertions • Declarative assertions (similar to modules) – applied in property checking. • Syntax: assert property (property_definition_or_instance) action action ::= [statement] | [statement] else statement Digitaalsüsteemide verifitseerimise kursus

18. SVA: declarative assertions, sequences • Declarative assertions describe temporal behavior • Main concept is a sequence: • Sequence = {(Bi,Ti),i V}, • Biis Boolean expression at time step Ti, and V is a set of integers (e.g. clock cycle index) Digitaalsüsteemide verifitseerimise kursus

19. SVA: sequnces and waveforms • SVA sequence constructor: ##N, where N is the delay • x ##4 z is equivalent to (x,t),(z,t+4) • Ranges can be described • E.g. x ##[1,3] z stands for x ##1 z or x ##2 z or x ##3 z • Many waveforms generally corresponding to a sequence! Digitaalsüsteemide verifitseerimise kursus

20. SVA: sequences and waveforms Digitaalsüsteemide verifitseerimise kursus

21. Analogy with Boolean functions Digitaalsüsteemide verifitseerimise kursus

22. SVA. Sequence Operators: AND • s1 AND s2 is true if s1 and s2 have both become true: Digitaalsüsteemide verifitseerimise kursus

23. SVA. Sequence Operators : OR • s1 OR s2 is true if s1 or s2 has become true: OR true true Digitaalsüsteemide verifitseerimise kursus

24. SVA. Sequence Operators: intersect • Similar to AND, but requires that the sequences begin and end at the same time: Digitaalsüsteemide verifitseerimise kursus

25. SVA. Sequence Operators: first_match • Is true when a sequence becomes true the first time: Digitaalsüsteemide verifitseerimise kursus

26. SVA. Operations: implication • S1  S2, i.e. ¬S1 + S1·S2 • If S1 becomes true at time t then start evaluating S2, whose result determines the result of the implication. • If S1 is false, then the implication is true. Digitaalsüsteemide verifitseerimise kursus

27. SVA. Sequence Operators: throughout • S = {(Bi,Ti),i V} • E throughout S is{(E ·Bi,Ti),i V} • E.g.(x1 + x2) throughout (##1 x3 ##2 x4) is equivalent to: (##1 (x1 + x2)x3 ##2 (x1 + x2)x4) Digitaalsüsteemide verifitseerimise kursus

28. SVA. Operatsioonid jadadega: within • s1 within s2 checks whether s1 is found in s2 and whether both sequences are true • s1 must begin after s2 begins and end after the end of s2! Digitaalsüsteemide verifitseerimise kursus

29. Assertion-based Verification • ABV benefits: • Dynamic – better observability detecting bugs earlier and closer to their origin • Static – better controllability direct verification to the area of interest

30. Assertion-based Verification • Completeness problem • Who/what and when should specify assertions? • When is it enough? • In practice design engineer writes them for VHS (Verification Hot Spots). Such spot: • contains a great number of sequential states; • deeply hidden in the design, making it difficult to control from the inputs • has many interactions with other state machines and external agents • has a combination of these properties

31. What assertions are? • Assertion is an asserted (=directive shows what to do) property (=a part of the DUT’ functional behavior) • speed-up • find out if anything went wrong earlier • improve quality (corner cases) • functional coverage • formal and dynamic verification • + assume, cover, expect, restrict…

32. What assertions are? Languages • PSL • next slide • SystemVerilog Assertions (SVA) – IEEE 1800 • a group of extensions to the Verilog HDL true[*0:$] ##1 !SOT ##1 SOT ##1 !ads1[*0:$] ##1 ads2 • OVL • Open Verification Library assertions • include PSL and VHDL checkers • A part of OVM/UVM from Mentor & Cadence • Synopsys: Open Vera Language assertions (OVA) • HDLs • assert statement s to print messages at the simulation console • severity levels • System C assertions, e, etc.

33. Label When to check reqack: assert always (req -> next ack); Property to be checked Verification directive What assertions are? PSL • Property Specification Language IEEE-1850 (2005) • Originated from Sugar (IBM), Accellera • Foundation Language (FL) • LTL, SERE • PSL Simple Subset for simulation • Time advances monotonically, it is finite, (operands restrictions) • Optional Branching Extension • CTL (for formal verification)

34. What assertions are? PSL (cont.) • Flavors: • SystemVerilog, Verilog , VHDL, SystemC, (GDL ?) • 4 layers • Boolean layer –Boolean expressions in HLD: (a&&(b||c)) • Boolean operators: AND, OR, -> • Temporal later – sequences of Boolean expressions over multiple clock cycles • Temporal operators (e.g. next_e, until, next_event) • invariance operators: always, never • SERE: ({A[*3];B}|->{C}) Sequential Extended Regular Expressions • Verification layer - directives for verification tool telling what to do with specified properties • assert, assume, cover, restrict • Modeling layer – models environment

35. What assertions are? LTL • Linear-Time (temporal) Logic (first introduced in 1981) • No branches, time is a path

36. What assertions are? CTL • Computational Tree Logic (first introduced in 1977) • branching-time logic, meaning that its model of time is a tree-like structure • there are different paths in the future, any one of which might be an actual path that is realized A[φUψ] == ( E[(ψ)U(φψ)] EG(ψ) ) • temporal operators: • A φ - φ has to hold on all paths (starting from the current state) • Eφ - there exists at least one path (-”-) where φ holds. • X φ - φ has to hold at the next state • G φ - Globally: φ has to hold on the entire subsequent path • F φ - Finally: φ eventually has to hold • φ U ψ - φ has to hold until at some position ψ holds • φ W ψ - Weak until: φ has to hold until ψ holds (= "unless".)

37. req req ack ack FAILED PASSED req ack NOT ACTIVATED What assertions are? Vacuity • Vacuity is a philosophical concept (not specific to PSL) • Vacuous passoccurs if a passing property contains Boolean expression that, in frames of the given simulation trace, has no effect on the property evaluation. vacuous pass

38. Assertion-based Verification