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Experiment 7:Using Embedded Microcontroller Cores to Implement Complex Digital Systems

Experiment 7:Using Embedded Microcontroller Cores to Implement Complex Digital Systems. Experiment 7: Top level view of the implemented circuit. STROBE. = PORTC(0). FPGA. PIC µController. CLK. RESET. PORTC. PORTB. PORTA. 7-Seg Decoder. Display. PORTA. PIC Microcontroller Core. MCLR.

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Experiment 7:Using Embedded Microcontroller Cores to Implement Complex Digital Systems

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  1. Experiment 7:Using Embedded Microcontroller Cores to Implement Complex Digital Systems ECE 449 – Computer Design Lab

  2. Experiment 7: Top level view of the implemented circuit STROBE = PORTC(0) FPGA PIC µController CLK RESET PORTC PORTB PORTA 7-Seg Decoder Display PORTA ECE 449 – Computer Design Lab

  3. PIC Microcontroller Core MCLR CLK PROGRAM PICROM 256 x 12 CONTROL UNIT P C 8 Addr Address Bus Data DATA 12 REGFILE R8 Instruction Decoder Fsel 8 4 8 R31 OPCODES FSR CONSTANTS Din Dout W ALU Data Bus 8 4 8 8 EXTENDED ALU COMPUTATIONS PORTA PORTB PORTC 4 8 8 ECE 449 – Computer Design Lab

  4. Flowchart of our PIC program RESET Set Port Directions Sum <= ‘0’ Counter <= ‘0’ Wait for a rising edge at Port C(0) Wait for a rising edge at Port C(0) Port B <= Sum(3 downto 0) N Port B <= Port A Sum <= Sum + Port A Counter <= Counter + 1 Wait for a rising edge at Port C(0) Counter = 8? Y Port B <= Sum(7 downto 4) ECE 449 – Computer Design Lab

  5. Selected Registers of PIC ADDR  Working Register (Accumulator) W  Program Counter PC 05 PORTA Bidirectional Input/Output Ports 06 PORTB 07 PORTC 08 R8 09 R9 R10 0A Register File (General Purpose Registers) . . 1E R30 1F R31  TRISA Direction Registers for Ports A, B & C  TRISB  TRISC ECE 449 – Computer Design Lab

  6. Selected PIC Instructions (1) MOVF f, d MOVF f, 1 f f <8,31> MOVF f, 0 k  <0,255> W MOVWF f MOVLW k W k MOVWF f MOVLW k f W ECE 449 – Computer Design Lab

  7. Selected PIC Instructions (2) 0 CLRF f CLRF f f f <8,31> 0 CLRW CLRW W ECE 449 – Computer Design Lab

  8. Selected PIC Instructions (3) INCF f, d f +1 INCF f,1 INCF f,0 W ECE 449 – Computer Design Lab

  9. Selected PIC Instructions (4) ADDWF f, d W f ADDWF f, 1 ADDWF f, 0 + ECE 449 – Computer Design Lab

  10. Selected PIC Instructions (5) ANDWF f, d W f ANDWF f, 1 ANDWF f, 0 and ECE 449 – Computer Design Lab

  11. Selected PIC Instructions (6) SWAPF f, d SWAPF f, 1 fH fL SWAPF f, 0 W ECE 449 – Computer Design Lab

  12. Selected PIC Instructions (7) GOTO label CALL label RETLW CALL label CALL label GOTO label label label label RETLW ECE 449 – Computer Design Lab

  13. Selected PIC Instructions (8) BTFSC f, b f 7 b 0 f(b) = 0? BTFSC f, b No Next instruction Yes After-next Instruction ECE 449 – Computer Design Lab

  14. Selected PIC Instructions (8) BTFSS f, b f 7 b 0 f(b) = 1? BTFSS f, b No Next instruction Yes After-next Instruction ECE 449 – Computer Design Lab

  15. Selected PIC Instructions (9) TRISB TRISA TRISC 8 8 4 TRIS f W TRIS PORTA TRIS PORTC TRIS PORTB 1 – Input port bit direction 0 – Output port bit direction ECE 449 – Computer Design Lab

  16. PIC Programming Environment Source File in the PIC Assembly Language *.ASM MPASM HEX File *.HEX *.LST Listing File MPSIM ECE 449 – Computer Design Lab

  17. Block RAMs Block RAMs Block RAMs in Spartan III FPGAs Configurable Logic Blocks I/O Blocks Block RAMs ECE 449 – Computer Design Lab

  18. Spartan-3 Block RAM Amounts ECE 449 – Computer Design Lab

  19. Block RAM Port Aspect Ratios used to implement PICROM 256x12 ECE 449 – Computer Design Lab

  20. Block RAM Port Aspect Ratios 1 2 4 0 0 0 4k x 4 8k x 2 4,095 16k x 1 8,191 8+1 0 2k x (8+1) 2047 16+2 0 1024 x (16+2) 1023 16,383 ECE 449 – Computer Design Lab

  21. Dual Port Block RAM ECE 449 – Computer Design Lab

  22. Dual-Port RAM 1024 x 18 RAMB4_S4_S16 • Each port can be configured with a different data bus width • Provides easy data width conversion without any additional logic WEA Port A In 1K-Bit Depth Port A Out 18-Bit Width ENA RSTA DOA[17:0] CLKA ADDRA[9:0] DIA[17:0] WEB Port B Out 18-Bit Width Port B In 1k-Bit Depth ENB RSTB DOB[17:0] CLKB ADDRB[9:0] DIB[17:0] ECE 449 – Computer Design Lab

  23. Dual-Port RAM used as 1024x18 ROM RAMB4_S4_S16 0 1 0 WEA ENA Clk_ROM Data[17:0] RSTA DOA[17:0] CLKA ADDRA[9:0] Addr[9:0] DIA[17:0] WEB All inputs of PORT B and data inputs of PORT A connected to 0 ENB Outputs of PORT B left unconnected RSTB DOB[15:0] CLKB ADDRB[7:0] DIB[15:0] ECE 449 – Computer Design Lab

  24. INIT_00 ADDRESS 014A 0F 0C0F 0E 0917 04 006A 03 0068 02 0006 01 0040 00 INIT_01 ADDRESS 0000 1F 0000 1E 014A 14 0C0F 13 03AA 12 0917 11 0026 10 INIT_0F ADDRESS 0000 FF 0000 FE 0000 F4 0000 F3 0000 F2 0000 F1 0000 F0 Initializing Block RAMs INIT_00 : BIT_VECTOR := X"014A0C0F09170A04076802A800260205002A01C5020A0917006A006800060040"; INIT_01 : BIT_VECTOR := X"000000000000000008000A1907070A1706070A020026014A0C0F03AA09170026"; INIT_02 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000"; …………………………………………………………………………………………………………………………………… INIT_0F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000") DATA ADDRESS Addresses are shown in redand data corresponding to the same memory location is shown in black ECE 449 – Computer Design Lab

  25. Contents of the Program Memory 16 bits stored ADDR 00 01 02 03 04 …. FD FE FF 0 0 4 0 0 0 0 6 0 0 6 8 0 0 6 A 0 9 1 7 ……. 0 0 0 0 0 0 0 0 0 0 0 0 256 memory locations 12 bits read ECE 449 – Computer Design Lab

  26. Experiment 7 ECE 449 – Computer Design Lab

  27. Experiment 7 – Part 1 RESET Set Port Directions Sum <= ‘0’ Counter <= ‘0’ Wait for a rising edge at Port C(0) Wait for a rising edge at Port C(0) Port B <= Sum(3 downto 0) Sum <= Sum + Port A Counter <= Counter + 1 N Wait for a rising edge at Port C(0) If PORT(C(1)=1) PortB<=Sum else PortB <= PortA Counter = 4? Y Port B <= Sum(7 downto 4) ECE 449 – Computer Design Lab

  28. Experiment 7 – Part 2 Implement PICREG Register File using Distributed RAM present in all CLB slices ECE 449 – Computer Design Lab

  29. CLB Slice Structure • Each slice contains two sets of the following: • Four-input LUT • Carry & Control • Storage element ECE 449 – Computer Design Lab

  30. Distributed RAM RAM16X1S D WE WCLK = O A0 A1 A2 A3 LUT LUT LUT RAM32X1S D WE WCLK A0 O A1 A2 A3 A4 or RAM16X2S D0 D1 WE = WCLK O0 A0 O1 RAM16X1D A1 A2 D A3 WE or WCLK A0 SPO A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3 • CLB LUT configurable as Distributed RAM • A LUT equals 16x1 RAM • Implements Single and Dual-Ports • Cascade LUTs to increase RAM size • Synchronous write • Synchronous/Asynchronous read • Accompanying flip-flops used for synchronous read ECE 449 – Computer Design Lab

  31. Experiment 7 – Bonus • Choosing maximum out of the entered • four numbers • 2. C program for an automated conversion of a PIC • .hex file to the sequence of initialization strings • for Xilinx Block RAMs: INIT_00, INIT_01, etc. ECE 449 – Computer Design Lab

  32. Questions? ECE 449 – Computer Design Lab

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