ECE-C662 [Knapp, “Behavioral Synthesis” Prentice-Hall 1996]

ECE-C662[Knapp, “Behavioral Synthesis” Prentice-Hall 1996] • HDL Descriptions • Behavioral Processes • Behavioral Compiler (BC) schedules processes but not concurrent statement • Use wait statements inside the process • Reset: insert a loop exit statement after each clock edge • Asynchronous resets Wait until (ck’event and ck=‘1’)or (reset’event and reset=‘1’);if reset=‘1’ then exit reset_loop;end if;

main : process variable i: integer; variable uk: signed(7 downto 0); begin reset_loop: loop uk1 := (others => '0'); uk2 := (others => '0'); wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; a1 := params; wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; a2 := params; wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if;

ready <= '1'; wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; outer: loop while (start /= '1') loop wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; end loop; wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; uk := din; ready <= '0'; yo1 := mult_2s(yk1, a1, clk);

for i in 0 to 1 loop -- latency wait until clk'event and clk = '1' ; if (reset = '1') then exit reset_loop; end if; end loop; dout <= yk(26 downto 19); wait until clk'event and clk = '1' ; if (reset = '1') then exit reset_loop; end if; while (start /= '0' ) loop wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; end loop;

wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; ready <= '1'; end loop outer; wait until clk'event and clk='1'; if (reset = '1') then exit reset_loop; end if; end loop reset_loop; end process main;

I/O modes • Cycle-fixed Mode • HDL specified I/O timing • BC does not schedule timing • Latency of straightline code • No single-cycle operation drives a multiple-cycle (e.g., memory access is multiple cycles) • Multiple-cycle can only drive output write • LoopsWhile (not ready) loop wait unitl ck’event and ck=‘1’;end loop;-- Illegal no waitdataout <= data;

While (not done) loop wait unitl ck’event and ck=‘1’;end loop;-- Illegal no wait While (not ready) loop wait unitl ck’event and ck=‘1’;end loop; • Superstate-fixed mode • Order of I/O operations omitting the number of clock cycles between operations • Rule 1. Any I/O write in a superstate goes in the last cycle • Rule 2. Any I/O read in a superstate can take place in any cycle in the superstate

While (not ready) looptmp := inport; -- I/O readwait until ck’event and ck=‘1’;wait until ck’event and ck=‘1’;outport <= data; --illegalend loop; • In the above Rule 1 is violated • Rule 3: Thisport <= something; -- illegal no wait loopthatport <= anything;wait until ck’event and ck=‘1’; end loop;

Rule 4: No I/O write between exit and the last clock edge before the exitBusy: While (strobe) loopwait unitl ck’event and ck=‘1’;thisport <= something; -- illegal If interrupt then exit busy end if; end loop; Storage := thatport;

IIR Filter synthesis reports and design optimization • Test bench • Reports • Timing Summary: 10 cycles of latency • Operation schedule • FSM • 8-cycle sample cycle • Reduce the latency in the for loop resulted in 5-cycle sample cycle • Decrease the clock period • From delay report the multiplication is the bottleneck • Use pipeline multiplier • 35 ns sample cycle and 5 cycle latency

ECE-C662 [Knapp, “Behavioral Synthesis” Prentice-Hall 1996]