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Team 2: Mind Readers

Krishna Jharjaria TJ Strzelecki Rick Schuman Matt Waldersen. Team 2: Mind Readers. Project Overview. The Mind Reader is a mobile brain-computer interface. Computer applications will be presented to the user through commercially available video glasses.

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Team 2: Mind Readers

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  1. Krishna Jharjaria TJ Strzelecki Rick Schuman Matt Waldersen Team 2: Mind Readers

  2. Project Overview • The Mind Reader is a mobile brain-computer interface. • Computer applications will be presented to the user through commercially available video glasses. • An EOG and commercially available EEG will be mounted inside of a common enclosure and will enable the user to navigate and select various applications. • A dsPIC microcontroller will be used to acquire the EOG and EEG signals, the EEG signals will be analyzed by an FPGA and a BeagleBoard XM will control the virtual reality environment as well as execute all of the computer applications

  3. Project-SpecificSuccess Criteria • An ability to encode/decode data packets from a NeuroSky EEG. • An ability for a user to select applications based on signals from a NeuroSky EEG. • An ability for a user to navigate between different applications on a display using EOG signals. • An ability for the system to interactively train the user to effectively operate the device. • An ability to display a live video stream from an external camera module, and integrate applications into the video system.

  4. Block Diagram

  5. Component Selection RationaleMicrocontroller • Considerations • Signal Processing abilities • Digital Communication pins • Optimized for C compiler • Processing speed • Resources and reference material • DSPIC33EP512MU810 • Extensive DSP Library with built in FFT function • 4-UART; 4-SPI; 2-I2C • Optimized for C compiler • ~53K of RAM • Large online community

  6. EOG Op-Amp Selection Rationale (TLC2272/4 & TLV2211 ) • Low Noise • Dual Polarity • Model Available in PSPICE • Multiple Op-Amp Models • Available in DIP and SMD configurations • With exception of the TLV2211 • High Accuracy

  7. EOG Op-Amp Selection Criteria

  8. ADC Selection Rationale (ADS1210) • High Resolution • 19.5 Effective Resolution (Bits RMS) • Differential input and 2.5V reference output eliminates need for virtual ground • Integrated Programmable Gain Amplifier • Integrated Digital Filter • Available in both DIP and SMD packages

  9. Component Selection Rationale FPGA Module • Considerations • Size (Logic Blocks) • Number of I/O Pins • Built in Functionality • Power Consumption • DLP-HS-FPGA3 USB - FPGA Module • 25,344 Logic Blocks (11,264 slices) • 63 Available user I/O channels • 32 Dedicated Multipliers, libraries for floating point arithmetic • FPGA module contains: regulators, clock generator, SDRAM, USB programmer, SPI Flash, compatible with Xilinx ISE WebPack • FPGA operates on 3.3V, sinks/sources approximately 24mA per I/O pin

  10. Component Selection Rationale BeagleBoardxM BeagleBoard-xM • 1.0 GHz ARM Cortex-A8 Processor • 512 MB RAM • 8 GB microSDHDD • libraries and main program • 4 USB 2.0 Slots • Mouse/Keyboard dev, Webcam • Expansion Header (Data Transfer) • o SPI • o UART • o I2C • o GPIO

  11. Packaging Design • Modular design • Maintains separation of digital circuitry and sensitive analog EOG circuitry • Enables the EOG circuitry to be placed as close possible to signal electrodes • Video glasses will be used in order to ensure that the video display is directly in front of the field of view • Light Weight Single Board Computer

  12. Packaging Design BeagleBoard-xM Size: 3.35” x 3.45” Weight: < 1 lb. Logitech C310 HD Cam 1280x720p frame capture < 8 oz. VuzixWrap 920 Twin 640x480p Display < 3 oz.

  13. Main Circuit Board FPGA and Beagle Board EOG inputs Power Supply Microcontroller Interface

  14. Power Supply 2 Switch Mode regulators 5V convertor For FPGA and Beagle Board 3.3 V convertor For Microcontroller 11.1V rechargeable Lithium ion Battery

  15. EOG inputs Connected to EOG via SPI Registered Jack (RJ11) Connected to EOG via SPI Logic Level convertor From 5V to 3.3V

  16. Micro, in-system-programmer, EEG Dongle, Oscillator In System Programmer Switch debouncer Pin 13 MCRL Pin 15 PGEC Pin 16 PGED Oscillator PCB mount Reset Through hole Reset Connections EEG input via UART

  17. UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) • Baud rate = 115200 bps • Specified by the NeuroSkyMindWave

  18. EEG signals FFT • EEG frequency range 4-7hz • Array size 512 • Output of the FFT resides in RAM • Inbuilt FFT API: FFTComplexIP() BitReverseComplex() SquareMagnitudeCplx() 4-7hz

  19. FPGA Module, Logic Level Converter, Beagle Board Switch debouncer Beagle Board 4 I/O for EOG 3 SPI pins for EEG FPGA Module Select button Logic Level Convertor From 3.3V to 5V 2x5 bit EOG input 4 bit EOG output Up, down, left, right

  20. PCB LayoutDesign Considerations Main Board Multiple Voltages needed Power Traces at least 40 mil, signal traces no smaller than 10 mil Isolate oscillator Physical location of connectors Decoupling Capacitors EOG Board Sensitive analog circuitry Distance between electrodes and filtering/amplification Physical size of EOG PCB

  21. PCB Layout

  22. PCB Layout – Main BoardFGPA Module

  23. PCB Layout – Main BoardFGPA Module

  24. PCB Layout – Main BoarddsPIC Micro

  25. PCB Layout – Main BoarddsPIC Micro

  26. PCB Layout – Main BoardPower Supply

  27. PCB Layout – Main BoardPower Supply

  28. PCB Layout – Main BoardEOG/SBC Connection & LLT

  29. PCB Layout – Main BoardEOG/SBC Connection & LLT

  30. EOG Theory of Operation • Electrooculography measures the signal given off of corneo-retinal potentials in the eyes • An EOG circuit consists of an instrumentation amplifier, amplifiers, low pass filtering and high pass filtering • A high pass filter is used to eliminate a naturally occurring DC drift • A low pass filter is used to remove all other external noise

  31. Instrumentation Amplifier Instrumentation Amplifier • High Input Impedance • Includes both a high pass filter to eliminate DC drift and a second order low pass filter

  32. Instrumentation Amplifier

  33. Sallen-Key 2nd Order LPF Sallen-Key 2nd-Order Low Pass Filter • Eliminates noise from external sources

  34. Sallen-Key 2nd Order LPF

  35. First Order LPF - Amplifier First Order Low Pass Filter – Amplifier Circuit • Eliminates noise as well as amplifies the signal

  36. First Order LPF - Amplifier

  37. Linear Regulator

  38. Voltage Inverter

  39. Analog-to-Digital Converter

  40. Reference Ground & Input Jack

  41. EOG Signal Conditioning Voltage (V) Time (s)

  42. EOG Signal Conditioning Voltage (V) Time (s)

  43. Normalizing EOG Signal ∆Voltage Sample Number

  44. Software Design/Development StatusArtificial Neural Network What is an Artificial Neural Network? Simplified mathematical model of the human brain Utilizes a network of “neurons” to model relationships between inputs and outputs How does a ANN work? ANN implement non-linear functions in each neuron This function sums weighted input values and passes them through a non-linear function, usually a Sigmoid function This output then propagates to further network layers for the process to be repeated Why use an FPGA implementation Highly parallel algorithm, with transistor like output Need for quick, complex calculations

  45. Software Design/Development StatusArtificial Neural Network

  46. Software Design/Development StatusArtificial Neural Network Basics of A Neuron Each neuron contains a number of synapses, one for each previous layer neuron connected A synapses will take inputs and multiply it by a predetermined specific weight The weighted values will then be accumulated and funneled into a nonlinear activation function (Sigmoid Function) Hardware Design Considerations Need multiple multipliers, one for each synapses (38 multipliers) Need to condense the size of a neuron Using control logic and multiple clock cycles we can lower the required multipliers to a single multiplier per neuron (12 multipliers) Implementation of non-linear Sigmoid Function Look-up Table

  47. Artificial Neural NetworkPreliminary Block Diagram

  48. Software Design/Development StatusArtificial Neural Network Where we proceed from here Training and testing of preliminary ANN using Matlab ANN toolbox This will allow the weighted values to be hardcoded into the FPGA Design and testing of single neuron in VHDL Development of a proven working topology

  49. Software Design/Development StatusHeads-Up Display • Tentative HUD Features • Webcam Live Feed • EEG Signal Data display • Home Screen • 3 x 3 application layout • Concentration to select app • Programs • Minimal key input • Closed apps return to Home

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