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Code Generation

Code Generation. Data Dependency Graph. (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8);. B3. a. b. c. d. e. Data Dependency Graph. (a) t1 := ld(x);

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Code Generation

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  1. Code Generation - Compiler Design and Optimization

  2. Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a CMPUT 680 - Compiler Design and Optimization

  3. b c d e Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a CMPUT 680 - Compiler Design and Optimization

  4. b c d e Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a f CMPUT 680 - Compiler Design and Optimization

  5. b c d e f g Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4:= t1 - 4; (e) t5:= t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4- t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a CMPUT 680 - Compiler Design and Optimization

  6. b c d e f g Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7:= t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a h CMPUT 680 - Compiler Design and Optimization

  7. b c d e f g Data Dependency Graph (a) t1 := ld(x); (b) t2 := t1 + 4; (c) t3 := t1 * 8; (d) t4 := t1 - 4; (e) t5 := t1 / 2; (f) t6 := t2 * t3; (g) t7 := t4 - t5; (h) t8 := t6 * t7; (i) st(y,t8); B3 a h i CMPUT 680 - Compiler Design and Optimization

  8. Position of code generator • Optional phase Intermediate code Intermediate code Code generator Code optimizer Front end CMPUT 680 - Compiler Design and Optimization

  9. Code Generation Problem: How to generate optimal code for a basic block specified by its DAG representation? If the DAG is a tree, we can use Sethi-Ullman algorithm to generate code that is optimal in terms of program length or number of registers used. CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 557)

  10. 1.Rearranging code(a+b)+(e+(c-d)) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 Generate code for a machine with two registers. - t4 Assume that only t4 is alive at the exit of the basic block. + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

  11. Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

  12. Example Assume that SUB only works with registers.  Can’t evaluate t3 because there are no available registers! t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

  13. Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

  14. Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 LOAD t1, R1 SUB R0, R1 STORE R1, t4 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

  15. Example t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD a, R0 ADD b, R0 LOAD c, R1 ADD d, R1 STORE R0, t1 LOAD e, R0 SUB R1, R0 LOAD t1, R1 SUB R0, R1 STORE R1, t4 1 spill - Evaluation Order: t1, t2, t3, t4 t4 + - t1 t3 e + a b t2 c d 10 instructions CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 558)

  16. Example(can we do better?) by changing evaluation order(rearranging the order) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

  17. Example(can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0,R1 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

  18. Example(can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

  19. Example(can we do better?) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 SUB R1, R0 STORE R0, t4 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

  20. Example(can we do better? Yes!!!) t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 LOAD c, R0 ADD d, R0 LOAD e, R1 SUB R0, R1 LOAD a, R0 ADD b, R0 SUB R1, R0 STORE R0, t4 no spills!!! - Evaluation Order: t2, t3, t1, t4 t4 + - t1 t3 e + a b t2 8 instructions c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

  21. Example:Why the improvement? We evaluated t4 immediately after t1 (its leftmost argument). t1 := a + b t2 := c + d t3 := e - t2 t4 := t1 - t3 - t4 + - t1 t3 e + a b t2 c d CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 559)

  22. Heuristic Node Listing Algorithm for a DAG (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; endwhile endwhile CMPUT 680 - Compiler Design and Optimization (Aho-Sethi-Ullman,pp. 560)

  23. We consider the unlisted interior nodes • 1 2 3 4 5 6 7 • Initially the only node with unlisted parent is 1 • Set n=1 • Now left child of 1 is 2 and parent of 2 is 1 which is listed. CMPUT 680 - Compiler Design and Optimization

  24. Hence list 2 • Set n=2 find left child that is 6 but 6 has unlisted parent 5 hence we cannot select 6 • We can now switch to 3. the parent of 3 is 1 which is listed one.. Hence list 3 set n=3 • The left of 3 is 4. as parent of 4 is 3 and that is listed hence list 4. left of 4 is 5 which has listed parent(i.e 4) hence list 5.similarly list 6. • As now only 7 is remaining from unlisted interior nodes we will list it. • Hence the resulting list is 1 2 3 4 5 6 7 . Then order of computation is decided by reversing this list. • 7 6 5 4 3 2 1 CMPUT 680 - Compiler Design and Optimization

  25. + - - + + c d e a b Node Listing Example 1  2 3 4  7 5 8 6 11 12 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT 680 - Compiler Design and Optimization

  26. + - - + + c d e a b Node Listing Example n 1  List: 1 2 3 4  8 5 7 6 11 12 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT 680 - Compiler Design and Optimization

  27. - + + c d e a b Node Listing Example 1  n List: 1 m 2 + - 3 4  8 5 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  28. - + + c d e a b Node Listing Example 1  n List: 1 2 m 2 + - 3 4  8 5 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  29. - + d e a b Node Listing Example 1  List: 1 2 n 2 + - 3 4  8 5 m + c 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  30. - + + c d e a b Node Listing Example 1  List: 1 2 3 n 2 + - 3 4  8 5 7 6 11 12 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT 680 - Compiler Design and Optimization

  31. - + + c d e a b Node Listing Example 1  List: 1 2 3 n 2 + - 3 m 4  8 5 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  32. - + + c d e a b Node Listing Example 1  List: 1 2 3 4 n 2 + - 3 m 4  8 5 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  33. + c d e a b Node Listing Example 1  List: 1 2 3 4 2 + - 3 n 4  m - + 8 5 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  34. + c d e a b Node Listing Example 1  List: 1 2 3 4 5 2 + - 3 n 4  m - + 8 5 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  35. d e a b Node Listing Example 1  List: 1 2 3 4 5 2 + - 3 4  n - + 8 5 m + c 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  36. d e a b Node Listing Example 1  List: 1 2 3 4 5 6 2 + - 3 4  n - + 8 5 m + c 7 6 11 12 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  37. d e Node Listing Example 1  List: 1 2 3 4 5 6 2 + - 3 4  - + 8 5 n + c 7 6 11 12 m a b 9 10 (4) while the leftmost child m of n has no unlisted parents, and is not a leaf node do /* since n was just listed, m is not yet listed */ (5) list m; (6) n := m; CMPUT 680 - Compiler Design and Optimization

  38. d e a b Node Listing Example 1  List: 1 2 3 4 5 6 8 2 + - 3 4  n - + 8 5 + c 7 6 11 12 9 10 (1) while unlisted interior nodes remain (2) select an unlisted node n, all of whose parents have been listed; (3) list n; CMPUT 680 - Compiler Design and Optimization

  39. d e a b Node Listing Example 1  List: 1 2 3 4 5 6 8 2 + - 3 4  - + 8 5 + c 7 6 11 12 9 10 Therefore the optimal evaluation order (regardless of the number of registers available) for the internal nodes is 8654321. CMPUT 680 - Compiler Design and Optimization

  40. The resulting list is 1234568. so the suggested order of evaluation is 8654321 . This ordering corresponds to the sequence of 3 address statements: • t8 = d + e • t6 = a + b • t5 = t6 – c • t4 = t5 * t8 • t3 = t4 – e • t2 = t6 + t4 • t1 = t2 * t3 • This will yield optimal code for the DAG in our machine whatever the number of registers, CMPUT 680 - Compiler Design and Optimization

  41. Optimal Code Generationfor Trees If the DAG representing the data flow in a basic block is a tree, then for some machine models, there is a simple algorithm (the SethiUllman algorithm) that gives the optimal order. The order is optimal in the sense that it yields the shortest instruction sequence over all instruction sequences that evaluate the tree. CMPUT 680 - Compiler Design and Optimization

  42. Sethi-Ullman Algorithm Intuition: 1. Label each node according to the number of registers that are required to generate code for the node. 2. Generate code from top down always generating code first for the child that requires the most registers. CMPUT 680 - Compiler Design and Optimization

  43. Sethi-Ullman Algorithm(Intuition) Left leaf Right leaves Bottom-Up Labeling: visit a node after all its children are labeled. CMPUT 680 - Compiler Design and Optimization

  44. Labeling algorithm generates optimal code for given expression in which minimum registers are used. • Labeling process starts from bottom to top. • Left leaf =1 right leaf=0 • If n has two children having label L1 and L2 resp • Then • Label(n) = max(L1,L2) if L1 <> L2 • L1+1 if L1=L2 • We start in bottom up fashion CMPUT 680 - Compiler Design and Optimization

  45. Labeling Algorithm CMPUT 680 - Compiler Design and Optimization

  46. Labeling Algorithm CMPUT 680 - Compiler Design and Optimization

  47. a b Example t4 t1 t3 e t2 c d CMPUT 680 - Compiler Design and Optimization

  48. a b Example Labeling leaves: leftmost is 1, others are 0 t4 t1 t3 e t2 0 1 1 c d 1 0 CMPUT 680 - Compiler Design and Optimization

  49. Example Labeling t2: Thus t4 t1 t3 a b e t2 0 1 1 c d 1 0 CMPUT 680 - Compiler Design and Optimization

  50. Example t4 t1 t3 a b e t2 0 1 1 1 c d 1 0 CMPUT 680 - Compiler Design and Optimization

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