Synopsys model

1. Synopsys model 溫家聖

2. Outline Design methodologies Synopsys model LEF_Abstract&Modify LEF file SOC encounter Stream in & Verification Homework

3. Outline Design methodologies Synopsys model LEF_Abstract&Modify LEF file SOC encounter Stream in & Verification Homework

4. Design methodologies • Full-custom • Starting from transistor circuits • Application Specific Integrated Circuits(ASIC) • Starting from HDL with support of standard cell library and logic synthesis tools • Cell-based design flow • FPGA • Starting from HDL with support of FPGA synthesis tools

5. Design Flow Specification Architecture Purchase Components Functional Description Functional Description Circuit Design Logic Synthesis Layout Auto Layout Generation Chip Assembly Physical Verification • Left fork • Full custom • Center fork • ASIC • Right fork • System on Chip

6. Full custom design flow Device Circuit Topology Size Transistors Simulation Layout Design Rule Check (DRC) Layout vs. Schematic(LVS) Parasitic Extraction(LPE) • Give the designer the most freedom • Lots of rope • Can be clever • Can huge yourselves too • For a specific function • Can achieve best performance • Speed , power, area, etc • Most work/time per function • Optimizations are at a low level • Circuit better be important • Think assembler, only worse

7. ASIC cell-based design flow Specification english Testbench and Vectors Functional Description(RTL) verilog vhdl Function Verification Design compiler(Synopsys) Primetime(Synopsys) Logic Synthesis Static Timing Place and Route Silicon Ensemble(Cadence) DRC LVS LPE • Separate teams to design and verify • Physical design is (semi-) automated • Loops to get device operating frequency correct can be troubling

9. Outline Design methodologies Synopsys model LEF_Abstract&Modify LEF file SOC encounter Stream in & Verification Homework

10. Synopsys model 編輯synopsys model (將synopsys model編輯成文字檔) Synopsys (產生database file) • 在cell-based設計流程下，使用Synopsys DC搭配自建元件合成電路 • 所需模組：提供library檔案(*.lib)，利用SYNOPSYS的library compiler編譯成db檔，載入*.db檔便可以合成

11. 建立synopsys model for each cells 我們可以建立cell之synopsys model，讓sysnopsys來合成我們所設計的電路，而如果要使用synopsys來synthesis circuit ，則至少必須有三種cell ，inverter ， nor 和nand，如果要合成序向電路則還需要DFF元件(需含有reset訊號腳位) 基本參數的設定：

12. >>geditmy_lib &

13. INV範例 Delay Cload=0.64 斜率為resistance intrinsic Cload=0.04 Cload

14. NOR範例

15. 下一步

16. >>dv & 執行synopsys Synosys model name Library name 元件庫名稱 成功後關掉 Command Window 建立好Synopsys後開dv在Command Window下執行 1. read_lib my_lib.lib 2. write_libmy_lib

17. 環境設定檔–指令:gedit .synopsys_dc.setup & • 作synopsys設定，檔案中設定的項目下所述 : • link_library: 解譯input 檔案敘述所使用的library • target_library: Design 所map 到的ASIC technology • symbol_library: 產生schematic 所需要用到的各種symbol view • search_path: 搜尋未定義的reference library 的路徑 • synthetic_library: 指定designwarelibrary • 其他Synopsys 所定義的變數設定

18. >>~/.synopsys_dc.setup& 範例檔案 如果我的的library 放在根目錄下 我們所建立的cell library 的名字為my_lib.db所其環境設定如下：

19. >>dv & Step1.啟動Synopsys Filesetup，作確認的動作

20. Step2.讀入Design 當檔案讀入時，會出現如果有error 或warning 之訊息, 會show 在此訊息框。 FileRead，將要作合成的*.v檔讀入

21. Step3.合成 DesignCompileDesignOK

22. Step4.確認是否有用到自建的元件

23. Step4.確認是否有用到自建的元件

24. Step5.合成結果分析(Area) DesignReportAreaOK

25. Step5.合成結果分析(Area) 這裡的單位：gate count， 因為之前元件庫裡的單位為gate count

26. Step5.合成結果分析(Delay information) TimingReport Timing PathOK

27. Step5.合成結果分析(Delay information) critical path

28. Step6.將合成後的結果存下(gatelevel檔) FileSave as*.gv/*.v檔