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Makefile. Script file to automate program compilation and linking (making) 1. Write the "makefile" 2. Write your programs 3. Run "make" or "make -f makefile" Makefile is a list of rules and commands http://www.gnu.org/software/make/. Makefile. Comments start with "#"
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Makefile • Script file to automate program compilation and linking (making) 1. Write the "makefile" 2. Write your programs 3. Run "make" or "make -f makefile" • Makefile is a list of rules and commands http://www.gnu.org/software/make/
Makefile • Comments start with "#" # This is a makefile for Hello World application • Variable definitions, usually in capital letters CC = gcc • Main target definition all: hello1.c • Dependency definitions %.o: %.c $(CC) $(CFLAGS) -c $< -o $@
Special Macros • $@ name of target • $? Name of depended changed • $< name of the first dependent • $^ names of all dependents
Inference rules • Generalized rule • Use % as a wild character %.o: %.c $(CC) $(CFLAGS) –c $< • Alternative way .c.o : $(CC) $(CFLAGS) –c $<
Makefile Example (1) #This file contains information used by a program called make to #automate building the program CFLAGS = -g -Wall CC = gcc LIBS = -lm INCLUDES = OBJS = a.o b.o c.o SRCS = a.c b.c c.c prog1.c prog2.c HDRS = abc.h
Makefile Example (2) all: prog1 prog2 prog1: prog1.o ${OBJS} ${CC} ${CFLAGS} ${INCLUDES} -o $@ prog1.o\ ${OBJS} ${LIBS} # The variable $@ has the value of the target. In this case $@ = prog1 prog2: prog2.o ${OBJS} ${CC} ${CFLAGS} -o $@ prog2.o ${OBJS} ${LIBS} .c.o: ${CC} ${CFLAGS} ${INCLUDES} -c $<