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TPS Timing System & Plan of Machine Protection System

TPS Timing System & Plan of Machine Protection System. Chun-Yi Wu TPS Control Team NSRRC, Hsinchu, Taiwan June 16, 2011. Outline. TPS Timing System Hardware Timing network Timestamp for TPS timing system Operation status of TPS linac timing Plan of Machine Protection System Hardware

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TPS Timing System & Plan of Machine Protection System

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  1. TPS Timing System&Plan of Machine Protection System Chun-Yi Wu TPS Control Team NSRRC, Hsinchu, Taiwan June 16, 2011

  2. Outline • TPS Timing System • Hardware • Timing network • Timestamp for TPS timing system • Operation status of TPS linac timing • Plan of Machine Protection System • Hardware • MPS network structure • Response time of fast protection system • Health check • Summary

  3. TPS Timing System

  4. TPS Machine Clocks Transfer to SR 3 GeV – BR Ext Energy Ramping t 150 MeV – BR Inj 333.333 msec BTS Linac LTB TRF = 2.00139 nsec TBR = TRF x 828 = 1.657 μs TSR = TRF x 864 = 1.729 μs Tcoinc = TBR x 24 = 39.768 μs Gun Booster Ring Storage Ring BR-CLK 0 24 SR-CLK 0 23 COINC-CLK Sync every 39 μs (24 turns of BR and 23 turns of SR)

  5. Timing System Selection • Event system is the most advanced timing system. • It adopt by many synchrotron light sources. • Performance and functionality are pretty well for synchrotron light source applications. • Select event system are very nature! • Form factor selection • TPS accelerator controls will adopt cPCI as standard EPICS platform. • Only 6U form factor will support for Phase I. • Negotiate with MRF to redesign the EVG/EVR. • Delivery of the first lot of event system module in late 2010. • First operation in Spring 2011 – delivery service for the TPS linac operation. • Distribution system • Long distance (~300 m): single mode fiber is most cost effective (> 100 m). • Short distance (< 50 m): OM3 multi mode fiber will be used.

  6. Timing System Hardware Fibre + Transceiver Fan-Out Concentrator cPCI-EVG-300 Universal I/O TTL Interlock Input ModuleUniversal I/O TTL Input UNIV-TTLIN Universal I/O TTL Output UNIV-TTL Universal I/O TTL Output Module w/ Delay Tuning Universal I/O NIM Output UNIV-NIM Universal I/O LVPECL Output Module Universal I/O LVPECL Output Module with Delay Tuning Universal I/O HFBR-1414 Output UNIV-HFBR-1414 Universal I/O HFBR-1528 Output UNIV-HFBR-1528 cPCI-EVR-300 cPCI-EVRTG-300 (e-Gun Trigger) Universal I/O modules GUN-RC-203/300

  7. TPS Phase I Timing modules GUN-RC-203 Gun Trigger Receiver Event Generator Fanout Concentrator Event Receiver Event Receiver with Gun Trigger and Fine Delay cPCI-EVG-300 cPCI-FOUT-CT-8 cPCI-EVR-300 cPCI-EVRTG-300

  8. Event Receiver (EVR) Event Receiver (EVR) Event Receiver (EVR) Triggers Triggers Triggers IRQ IRQ IRQ 8 8 8 Clocks Clocks Clocks Structure of TPS Timing System Event Generator (EVG) Sequence RAM 0x2A …….. 0x28 …….. 0x26 …….. 0x24 …… 0x22 …… 0x20 Mains 60 Hz Sync RF 499.654 MHz RF/4 Dividers 8 Ext Triggers (1PPS, 1 MHz, Beam Loss, Beam Abort …) Registers Optical Fan out concentrator 8 bit Ext Bus Serializer & Transmitter

  9. cPCI-EVG-300 499.654 MHz 124.9135 MHz RF Master Oscillator Divide by 4 Multiplexed counter 0 Booster revolution clock generation ( 207) 603.445 kHz • 20 (3 Hz) • 24 (2.5 Hz) • 30 (2 Hz) • 40 (1.5 Hz) • 60 (1 Hz) Multiplexed counter 1 SR revolution clock generation ( 216) 0 AC mains voltage Transformer 60 Hz) Divide by 1 to 256 D i s t r i b u t i o n B i t s 1 578.303 kHz 2 Rep. rate Orbit Feedback Time Tick 3 SR: 864 = 25 x 33 = 22 x 32 x 24 = 4 x 216 578.303 KHz (1729.197 nsec) BR: 828 = 22 x 32 x 23 = 4 x 207 603.445 KHz (1657.147 nsec) Coincident Freq 4 x 4968 25.14 KHz (39.772 ms) Phase shift (delay) 0 to 25.5 msec Beam Trip Command 4 Multiplexed counter 7 Coincidence clock generation ( 4968) 5 Fiber Optic Link 6 Synchronize to Coincidence clock 7 Optical Transceiver Sequence RAMs alternate. One event RAM may be modified while the other one is active sending events to control injection. 25.14 kHz (39.772 ms) Event Frame Event Priority Encoder 125 MEvents/sec Sequence RAM 1 Event Code Trigger Sequence RAM 2 SR: 518.4 m BR: 496.8 m Trigger Event 0~7 EVR (Uplink Event) Distributed Bus 0~7 Univ Input 1~12 Universal Input x Mapping Registers External Interrupt Trigger IN

  10. cPCI-EVR-300 Trigger IN Set Set S S F/F F/F Trigger Trigger S S Delay Delay Pol Pol Event CLK Event CLK C C Width Width Reset Reset C C Front Panel Input Mapping Registers Uplink Logic Recovered Event Clock Trigger OUT Clock Recovery Univ Output 0, 1 Distribution Bus Data 8 bit Univ Output 2, 3 UnivOutMapx Registers Univ Output 4, 5 2 K Data Buffer De- Serializer Univ Output 6, 7 Optical Fiber from EVG Univ Output 8, 9 Event Mapping (RAM) Events 8 bit Univ Output 10, 11 cPCI Interface

  11. cPCI-EVRTG-300 Set Set S S F/F F/F Trigger Trigger S S Delay Delay Pol Pol Event CLK Event CLK C C Width Width Reset Reset C C UnivOutMapx Registers Recovered Event Clock Trigger OUT Clock Recovery Univ Output 0, 1 Distribution Bus Data 8 bit Univ Output 2, 3 GTX4 Pulse Mode Frequency Mode Pattern Mode Diff OUT 2 K Data Buffer GTX5 Pulse Mode Frequency Mode Pattern Mode De- Serializer Diff OUT Optical Fiber from EVG Fiber OUT GTX6 Pulse Mode Frequency Mode Pattern Mode GUN-TX-203 Mode SFP Event Mapping (RAM) Events 8 bit Fiber OUT GTX7 Pulse Mode Frequency Mode Pattern Mode GUN-TX-203 Mode SFP cPCI Interface

  12. Fanout Concentrator Fanout Concentrator Fanout Concentrator Fanout Concentrator Fanout Concentrator Timing System Distribution Fanout Concentrator 1st level x 1 2nd level x 4 3 rd level x 24 Total 29 units Master RF Frequency Standard • The propagation delay time due to fiber is ~5 ns/m. • In order to achieve almost simultaneous receipt of event codes at EVRs. All fiber lengths are equal. EVG Timing Master EVR-300 Linac Trigger EVRTG-300 Gun Trigger EVR-300 Uplink CIA 01 Fanout Concentrator EVR-CIA01 Drift Compensator CIA 02 Fanout Concentrator EVR-CIA02 EVR-Booster PS EVR-RF 1 350 Meter Signal Mode Fiber EVR-RF 2 60 Meter OM3 Fiber EVR-RF 3 EVR-Booster RF CIA 23 Fanout Concentrator EVR-BBF EVR-Linac EVR-CIA24 EVR-LTB/BTS Diag CIA 24 Fanout Concentrator EVR- Injection/Extraction #1 400 Meter environmental temperature sensing OM3 Fiber EVR- Injection/Extraction #2 EVR-CIA EVR-CSCR

  13. Time reference for TPS control system GPS Antenna 1 PPS TPS Control Network Rubidium Frequency Standard NTP server 10 MHz UTC “Second” 1 PPS TPS Timing Network 499.654 MHz RF Distribution EPICS IOC 1 MHz RF Mains 60 Hz EVG “Second” Event Generator DBUS5 Trigger Events 0x70 0x71 Beam loss 0x44 MPS 0x45 CPU cPCI EPICS IOC CPU Fanout EVR EVR Triggers, Interlock Input Triggers/Clocks Output Triggers/Clocks Output

  14. Possibility to use cPCI-EVG-300 generate “SECOND” events cPCI or VME64x Bus Host CPU can acquire UTC second from NTP server at system boot time or anytime when need. Set by the host CPU on-demand (system boot, cold start) “Second” Register External 1PPS Load “Second” Counter τ Count Up Clock Load τ “Second” Shift Register Bit 0 Clock Generator Existed EVG core 0x70 Tx Rx Embedded in EVG Core 0x71

  15. Planned Beamline Timing Interface Control Network + Timing Network Fiber Link to nearby CIA (4 Pairs OM3 Fiber) fRF or fRF/N, N = 4,5,6 ? Fiber Patch Panel Control Network ~ 300 m Fiber Link (with/without drift compensation) EPICS IOC cPCI-EVRTG-300 Standard Supports Dedicated Fiber Link (Option) Jitter Cleaner (Option) UNIV I/O 0 (TTL or NIM) Short Gate UNIV I/O 3 (TTL or NIM) SR Clock UNIV I/O 5 (PECL) RF Clock UNIV I/O 1 (TTL or NIM) Long Gate UNIV I/O 4 (TTL or NIM) Spare Low Jitter Clock ( < 100 fsec ?) UNIV I/O 5 (PECL) RF Clock Commercial fs Locker 5 ~ 20 ps Trigger or Clock (dependent on modules used) ~ 30 psec drift (worst case) for a few degree of ambient temperature variation (without drift compensation) (< 500 fs) Synchrolock-AP, FEMTOLOCK, etc.

  16. GUN-TX-203 Mode - Operation Scheme cPCI-EVRTG-300 (SFP port, GTX6 or GTX7 ) External inhibit Iuput Pulse Generator Output Modulator Micrel SY100EP196 Delay Line 1024 step ~ 9 psec/step Transceiver Tx Rx Recovered Event Clock Event Clock Phase Shifter 0, 2, 4, 6 nsec To GUN-RC-203 RF CLK Trigger Width Delay Encoded Clock Fiber Link Delay ≡ 8 nsec step (Pulse Generator) + 2 ns (Phase Shifter) + 10 ps step (Delay Line) Width ≡ multiple of event clock period 8 ns (Pulse Generator) UNIV-TTLIN-IL@UNIV0/1 for inhibit GUN-RC-203 (one channel) Pulse Out Transceiver Encoded Clock Rx Demodulator Tx Encoded Clock Pulse Out

  17. TPS E-Gun Trigger Options Single Bunch < 1 nsec Current Multi Bunch with 500 MHz Modulation MRF GUN-RC-203 2 nsec Current 50 ~ 1000 nsec Arbitrary bunch pattern ? MRF GUN-RC-300 2 nsec Current 50 ~ 1000 nsec We still consider e-gun trigger need to support arbitrary bunch pattern or not?

  18. Prototype Operation GUI Timing MasterPrototype TPS Main GUI TPS Timing Summary page E-Gun Trigger module

  19. EVG/EVR/EVRTG Configuration pages

  20. Preliminary Jitter Measurement of Timing System cPCI-EVR-300 TTL output Module vs. RF < 20 ps LTB FCT #1 (Linactest site ) Single Bunch Beam FCT #1 vs. RF < 10 ps

  21. Planof Machine Protection System

  22. Machine Protection System – Purpose • Latch input event • Transmit the input event to somewhere • Apply interlock rules and activate actuator • Reset the latch after the input event removed

  23. Global Machine Protection System (MPS) PLC Network • Redundancy dual loop can be installed later or necessary • Economic design by heavily used remote I/O • Heartbeat ensure system is alive Cost Saving Design EPICS CA access (read status, interlock reset, ~ 100 msec response time) Cell # 23, 24 Interlock PLC Sub Unit Cell # 21, 22 Interlock PLC Sub Unit • Strategic to achieve high reliability • High reliable PLC • Heart beat • Redundancy • Failsafe TPS SR PLC with Embedded EPICS IOC Cell #1,2 Interlock PLC Main Unit Beam position interlock Beam trip interlock RF status Interface to the safety/interlock which are responsible various groups … Cell # .. Interlock PLC Sub Unit TPS Booster Cell # .. Interlock PLC Sub Unit Cell # .. Interlock PLC Sub Unit Intra-PLC Communication Link Fiber-optic FA Bus Type 2 ( ~ 2 msec response time) Trip beam command, post-mortem trigger, …etc. (to event system) Cell # .. Interlock PLC Sub Unit Cell # .. Interlock PLC Sub Unit Cell # .. Interlock PLC Sub Unit

  24. Configuration of MPS PLC Communication link F3LR02-ON Link module Main Unit PLC 300 m Fiber Sub Unit (Remote I/O) 300 m Fiber 10 m Fiber CIA 1 CIA 13 CIA 18 CIA 19 CIA 24 CIA 4 CIA 7 CIA 12 50 m Fiber CIA 14 CIA 17 CIA 20 CIA 23 CIA 2 CIA 5 CIA 7 CIA 11 CIA 15 CIA 16 CIA 21 CIA 22 CIA 3 CIA 6 CIA 8 CIA 10

  25. TPSFast Protection System • TPS timing system can be used to transmit fast event to actuator. • EVR modules have uplink event generation capability. • Fan out concentrator modules can concentrate signals form eight EVRs/downstream and forward the signals upstream. • EVG module has external input to enable 8 event triggers. Fast Protection system Fast event (Trip RF signal) Timing system EVR Timing system EVR Actuator (RF station) Slow Protection system MPS system PLC MPS system PLC

  26. It’s necessary to measure the time delay of fast protection system . Time delay come from Fiber optic propagation time and timing system processing time Optical fiber propagation time is around 5 ns/m. Processing time depends on EVG/EVR/Fan-out concentrator modules. Response Time of TPSFast Protection System

  27. Measure Response Time of TPSFast Protection System 2 MPS-Trip Out MPS-Trip (decode Uplink Event) EVG EVR1 5 m(fiber) FOUT-CT 10 m(fiber) Delay(EVR1)： 2.45 μs (Uplink) Delay(EVR2)： 4.42 μs (Downlink) FOUT-CT 310 m (fiber) Uplink 1 < 5 μs response time MPS-Trip In 2 FOUT-CT 3 MPS-Trip Out (EVR2) 10 m(fiber) EVR2 1 3 MPS-Trip Out MPS-Trip In

  28. Machine Protection System – Event Input Board • Input from • Magnet Thermostat • Beam Line dump beam • Front End dump beam • Vacuum dump beam • Orbit interlock • DCCT failed • Heartbeat • …… • Output to • MPS PLC • Fast protection system(Timing system) • cPCI EPICS IOC • Latch/Reset event function

  29. Machine Protection System – Actuator Output Board • Input from • MPS PLC • Fast protection system (Timing System, TTL) • cPCI EPICS IOC (Contact, TTL or 24 V) • Contact output to (~ a few ms response time) • e-gun inhibit • RF inhibit ? • …. • Open collector output to(~ μs response time) • RF inhibit ? • Heartbeat • Power supply of magnets inhibit • …..

  30. Role of the Heartbeat check on Actuator Output Board EPICS IOC DO Timing EVR Output MPS PLC DO Heartbeat Machine Protection System Actuator Output Board Actuator output will be normal when heartbeat is normal! Actuator output will be failed when heartbeat stop! To Actuator

  31. Summary • TPS timing system • The first lot of EVG/EVR/Fan-out concentrator modules was received in December 2010 • Setup test system has been started from February 2011 • Linac timing is ready for commissioning of the TPS linac in April 2011 • cPCI-EVR-300 jitter w.r.t. RF clock < 20ps • cPCI-EVRTG-300 jitter w.r.t. RF clock < 10ps • Other issues are being planned • Beam Injection/Top up mode Injection • Timestamp • …. • Machine protection system • Provide MPSPLCsystem(~few ms) and fast protection system(<5us) • Need to • Define and implement MPS interlock logic • Low level Interface definition and specification • Prototype manufacture

  32. Thanks for Your Attention! 32

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