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The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs

The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs. Joseph Fabula Jason Moore Austin Lesea Saar Drimer. This work has benefited from the use of the Los Alamos Neutron Science Center at the Los Alamos National Laboratory. This facility is funded by the

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The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs

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  1. The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs Joseph Fabula Jason Moore Austin Lesea Saar Drimer This work has benefited from the use of the Los Alamos Neutron Science Center at the Los Alamos National Laboratory. This facility is funded by the US Department of Energy under Contract W-7405-ENG-36. MAPLD2004

  2. Objectives of this Study • Measure the neutron single event upset cross section of various current CMOS processes - Utilizing accelerated neutron beams to: • Test the upset potential of the static latches in FPGAs and CPLDs • Test the upset potential of the flash storage cells in CPLDs - Utilizing applications atmospheric based tests to • Test the upset potential of the static latches in FPGAs • Calibrate the results of accelerated beam testing • Compare findings with other independent researchers Fabula_139

  3. Test Facilities Used • Accelerated Testing • Los Alamos Neutron Science Center • Hess spectrum accelerated neutron beam • Energy levels 1.5 to 600 MeV • Applications Testing (natural flux) • Xilinx San Jose – sea level • Xilinx Albuquerque – 5,200 feet • White Mountain Research Center – 12,000 feet • Mauna Kea Observatory – 13,500 feet Fabula_139

  4. Devices Tested • Virtex II FPGA • XC2V6000 • 150 nM CMOS Static-Latch based technology • Virtex II-Pro FPGA • XC2VP4 and XC2VP7 • 130 nM CMOS Static-Latch based technology • Spartan 3 FPGA • XC3S100 • 90 nM CMOS Static-Latch based technology • XPLA3 (CoolRunner I) CPLD • XCR3256XL • 350 nM CMOS FLASH based technology • CoolRunner II CPLD • XC2C256 • 150 nM CMOS FLASH based technology Fabula_139

  5. FPGA Test Fixtures Virtex II Virtex II-Pro Spartan 3 Fabula_139

  6. CPLD Test Fixtures Fabula_139

  7. How we tested NSEU Sensitivity • Accelerated Testing vs Atmospheric Testing • Accelerated • Testing with Spallation Neutron sources • LANSCE spallation spectrum matches atmospheric neutrons • LANSCE source gives ~ 105 to106 acceleration • Atmospheric • We can use the natural radiation environment around us • Due to low rates, a very large number of devices are required • Testing times can be very long (many month to years) • Acceleration (up to 10X) is achievable by testing at altitude(s) • However, this test is the ultimate correlation for all accelerated tests • references • JEDEC Standard (JESD89) “Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray- Induced Soft Errors in Semiconductor Devices” • IEC TC107-AR-8 (draft currently) Avionics Processes Fabula_139

  8. Virtex II Accelerated Data Fabula_139

  9. Virtex II-Pro Accelerated Data 2VP4 2VP7 Fabula_139

  10. Spartan 3 Accelerated Data Fabula_139

  11. CPLD (Flash) Accelerated Data XCR3256XL (350 nM) XC2C256 (150 nM) Fabula_139

  12. Summary Accelerated Test Results Static Latch Upset Results Flash Storage Upset Results This work has benefited from the use of the Los Alamos Neutron Science Center at the Los Alamos National Laboratory. This facility is funded by the US Department of Energy under Contract W-7405-ENG-36. Fabula_139

  13. Rosetta NSEU Testing • What is Rosetta? • Atmospheric Test started in 7/2002 • Rosetta stone provided correlation between languages/scripts. Rosetta experiment provides correlation to LANSCE test results • System of 100 2V6000s • Runs 24/7/365 – Internet Monitored • Read back and error logging 12 times a day • Each test contains >1.9 Gbits of config latches • Test operating at 4 altitudes • Sea Level – San Jose • 5,200 feet – Albuquerque • 12,000 feet – White Mountain Research Center • 13,500 feet – Mauna Kea Observatory • Additional testing started for VII-Pro (130 nM) and for Spartan-III (90 nM) Fabula_139

  14. Rosetta Board 100 XC2V6000 1.9 Gbits Fabula_139

  15. Rosetta Test Results • Data shown is accurate as of 5/6/04 • 3.18e6 total device hours • Rosetta/LANSCE correlation factor is 1.51 • LANSCE is predicting worse results by a factor of 1.51 Fabula_139

  16. Appendix

  17. Logic Failures vs SEUs(SEUPI) • Is there a difference? YES • An SEU does not necessarily cause a functional failure • Many Configuration Bits are not used • 90% of the FPGA is routing! • Example • Proton test of a V300 • Two methods to evaluate: • Method 1: • Total Upsets / # 1 bit failures • 437/8 = 54.6 • Method 2: • Total Upsets / # failures • 437 / 69 = 6.3 • Conservatively, we use a factor of 10 (SEUPI factor) Fabula_139

  18. Logic Failures vs SEUs(SEUPI) • Independent Confirmation • Work by BYU and LANL indicated that the logic upset multiplier can be as high as 25 - 100 for specific designs in a V1000 • By logical extension, the larger the FPGA the higher the multiplier for any given logic implementation • BYU and LANL have developed a bit flip logic impact simulator for the V1000 that has been verified in Proton testing • Xilinx has extensive data on PIP utilization from the many EasyPath applications that we are supporting • Xilinx laboratories are developing software algorithms (SEUPI) to identify “critical” bits which may affect user logic • SEUPI analysis of specific customer applications has shown SEUPI factors from 10 to 80 with an mean of 42 Fabula_139

  19. Comparison with Independent Data • Actel commissioned IROC to independently test various FPGAs for NSEU Effects • IROC tested Xilinx, Altera and Actel products • Test design was “n” 16x16 bit multipliers whose values were muxed to a common output. Mux line was 7 bits -> up to 128 multipliers supported • Pure combinatorial logic – no FFs! • “Focus was on configuration memory only” Fabula_139

  20. IROC Analysis • Results • IROC unquivocally stated that Xilinx FPGAs do not exhibit NSEL (Neutron Single Event Latch), a potentially destructive effect seen in some recent ASICs and RAMs • IROC confirmed the existence of the SEUPI factor in Xilinx FPGAs – even though it was only in one design: • VII (14MeV test) = 6.67 • VII (LANSCE) = 10 • S3 (LANSCE) = 4.54 • Reverse engineering of the IROC data confirmed Xilinx contention that the per-bit cross-section was improved by Xilinx in their 90nm technology vs their 150nm technology (see next slide) Fabula_139

  21. IROC Analysis • 150nm (V-II) vs 90nm (S-3) • Using IROCs data for the Number of SEUs and the Fluence (n/cm2) we can calculate the per-bit cross-section difference between technologies • Conclusion: S-3 (90 nM) cross-section is smaller! Fabula_139

  22. Conclusions • LANSCE data provides good correlation with atmospheric testing when the correct energy model(s) are used • ROSETTA data indicates clear support for using the >10.0 MeV model for current process technology • Independent IROC data confirmed three of Xilinx key assertions, namely: • The sky is not falling as technology continues to shrink below 220 nM (Moore’s law still lives and our designers are smart) • Xilinx logic upset rates are greatly improved due to the documented SEUPI factor • Xilinx FPGAs do not exhibit Neutron Single Event Latch-up • The neutron cross sections have been stabilized as technology shrinks (compensating a sensitivity increase by a probability decrease function) • Xilinx designers are increasing the robustness of our state of the art static latches to the effects of atmospheric neutron flux • Current generations of Flash storage cells continue to be immune to neutron upset Fabula_139

  23. Virtex II MTBF Calculations • Failure defined as incorrect operation of the FPGA • Time to Configuration Upset (Config Upset) = 1 / (# bits * Neutron Cross-Section (LANSCE) * Neutron Flux) • Config Upset Rosetta = Rosetta factor applied • Logic Upset = SEUPI factor applied • Ignoring the SEUPI factor is inaccurate! – you don’t use every configuration memory cell in an FPGA. Calculations are at sea level = 14.4n-cm2/hr flux; Rosetta Factor = 1.5, SEUPI Factor = 10 Fabula_139

  24. Effects of Altitude • Virtex-II MTBF Calculations at 40K feet • Assumptions: • Neutron Flux of 3060 n-cm2/hr@ 40,000 feet • Rosetta Factor of 1.5 • SEUPI Factor of 10 Fabula_139

  25. Spartan 3 MTBF Calculations • Failure defined as incorrect operation of the FPGA • Time to Configuration Upset (Config Upset) = 1 / (# bits * Neutron Cross-Section (LANSCE) * Neutron Flux) • Config Upset Rosetta = Rosetta factor applied • Logic Upset = SEUPI factor applied • Ignoring the SEUPI factor is inaccurate! – you don’t use every configuration memory cell in an FPGA. Calculations are at sea level = 14.4n-cm2/hr flux; Rosetta Factor = 1.5, SEUPI Factor = 10 Fabula_139

  26. Effects of Altitude • Spartan 3 MTBF Calculations at altitude • Assumptions: • Neutron Flux of 3060 n-cm2/hr @ 40,000 feet • Rosetta Factor of 1.5 • SEUPI Factor of 10 Fabula_139

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