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Lecture #39

OUTLINE The MOSFET: Sub-threshold leakage current Gate-length scaling. Lecture #39. We had previously assumed that there is no channel current when V GS < V T . This is incorrect.

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Lecture #39

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  1. OUTLINE The MOSFET: Sub-threshold leakage current Gate-length scaling Lecture #39 EE130 Lecture 39, Slide 1

  2. We had previously assumed that there is no channel current when VGS < VT. This is incorrect. If fS > fF, there is some inversion charge at the surface, which gives rise to sub-threshold current flowing between the source and drain: Sub-Threshold Leakage Current EE130 Lecture 39, Slide 2

  3. Sub-Threshold Slope S EE130 Lecture 39, Slide 3

  4. How to minimize S? EE130 Lecture 39, Slide 4

  5. MOSFET Scaling • MOSFETs have scaled in size over time • 1970’s: ~ 10 mm • Today: ~50 nm • Reasons: • Speed • Density EE130 Lecture 39, Slide 5

  6. Benefit of Transistor Scaling • IDS as L  (decreased effective “R”) • Gate area  as L  (decreased load “C”) • Therefore, RC  (implies faster switch) EE130 Lecture 39, Slide 6

  7. Circuit Example – CMOS Inverter EE130 Lecture 39, Slide 7

  8. td is reduced by increasing IDsat EE130 Lecture 39, Slide 8

  9. Constant-Field Scaling • Voltages and MOSFET dimensions are scaled by the same factor k>1, so that the electric field remains unchanged EE130 Lecture 39, Slide 9

  10. Constant-Field Scaling (cont.) • Circuit speed • improves by k • Power dissipation • per function • is reduced by k2 EE130 Lecture 39, Slide 10

  11. VT Design Trade-Off • Low VT is desirable for high ON current: IDsat (VDD- VT) 1 <  < 2 • But high VT is needed for low OFF current: log IDS Low VT • VT cannot be scaled aggressively! High VT IOFF,low VT IOFF,high VT VGS 0 EE130 Lecture 39, Slide 11

  12. Since VT cannot be scaled down aggressively, the power-supply voltage (VDD) has not been scaled down in proportion to the MOSFET channel length EE130 Lecture 39, Slide 12

  13. Generalized Scaling • Electric field intensity increases by a factor a>1 • Nbody must be scaled up by a to control short-channel effects • Reliability and • power density • are issues EE130 Lecture 39, Slide 13

  14. CMOS Scaling and the Power Crisis 1E+03 Active Power Density 1E+02 1E+01 1E+00 Power (W/cm2) 1E-01 1E-02 Passive Power Density 1E-03 1E-04 1E-05 0.01 0.1 1 Gate Length (μm) • Lg/VDD/VT trends  increases in: • Active Power Density (VDD2)~1.3X/generation • Passive Power Density (VDD)~3X/generation • Gate Leakage Power Density>4X/generation EE130 Lecture 39, Slide 14 Source: B. Meyerson, IBM, Semico Conf., January 2004

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