Digital Logic & Circuits: Basics, Gates, Implementations

1. מבנה מחשב תרגול 2

2. Boolean AND Operation Truth Table Equivalent Gate Different notations:

3. Boolean OR Operation Truth Table Equivalent Gate Different notations:

4. Boolean NOT Operation Truth Table Equivalent Gate Different notations:

5. Boolean NAND Operation Equivalent Gate Truth Table

6. Boolean NOR Operation Equivalent Gate Truth Table

7. Boolean XOR Operation Truth Table Equivalent Gate Different notations:

8. How to implement XOR? Which is Better?

9. Example • What does the following combinational circuit decide ?

10. Boolean Equalities (1) • Rules of Associativity, Commutation. • Other rules:

11. Boolean Equalities (2) • Distribution • deMorgan

12. Example (1):Simplify the expression Compare number of gates

13. Example (2):Simplify the expression

14. 1 1 Evaluating an Expression (1) • Let’s look at the first expression: 1 1 1

15. 1 1 1 Evaluating an Expression (2) • Let’s look at the first expression: 1 =1

16. We get Different Notation for Truth Table 0 0 0 0 1 0 1 0 1 1 1 2 0 0 0 3 1 1 0 0 1 4 0 1 0 1 1 0 1 5 1 6 1 0 0 1 7 1 1 1

17. Disjunctive Normal Form 0 0 0 0 1 It’s easy to transform a DNF formula to its equivalent gates’ representation 0 1 0 1 1 1 4 0 1 0 1 1 0 1 5 1 1 7 1 1

18. Disjunctive Normal Form

19. New Components • Two major components of combinational logic are – multiplexors & decoders. • 2-input multiplexor (or selector) is implemented with gates below a b a b c c s s gate implementation symbol

20. Multiplexors (MUXes) • A device that selects one of several input signals and forwards it into a single line. • Also called a data selector

21. c Multiplexors (MUXes) s 0 1 2 3 4 5 6 7 • Multiplexors can have any number of inputs (in theory) • Multiplexors can apply to buses  multiplied for many lines. • Example: 1 x 2 multiplexor on 32 bits bus. a31 b31 M c31 a30 b30 3 X 8 multiplexor c30 M s2 s1 s0 . . . . . . 32 a b 32 c a0 b0 M c0 32 symbol s

22. Encoders • An encoder conv-erts information from one format to another. For the purposes of speed, secrecy, security, or saving space by shrinking size.  2n input lines, and at most only one of them will ever be high, produces n-bit output lines. ( Other options – don’t cares )

23. Decoders • Reverse operation of an Encoder undoing the encoding so that the original information can be retrieved • Combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. • The same method used to encode is usually just reversed in order to decode. • Results in sending less information !!!

24. 0 1 2 3 4 5 6 7 0 1 2 DECODER Decoders 3 X 8 Decoder Each combination of the inputs enables exactly one output

25. Adders • A digital circuit that performs addition of numbers. • The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). • The carry signal represents an overflow into the next digit of a multi-digit addition.

26. a b sum Cout Cin a b sum Cout Full Adder from Half Adders Half adder Full adder from 2 half adders + or gate We will look into adders more closely when we examine the ALU

27. Flip-Flops • What happens if we create a circle in the logic gates diagram? • a Circuit that has two stable states and can be used to store state information. • Can be made to change state by signals applied to one or more control inputs. This is a S-R Flip-Flop

28. R=0 S=1 R=0 S=0 Q=1 Q=1 Q=1 Q=0 Q=1 Q=0 Q=0 • An S-R flip-flop: • S – set. R Reset. Initial state Q=1 and • R = 0 S = 1 : Changes Q to 1. R = 1 S = 0 : Changes Q to 0. R=1 S=0 R=0 S=0 Q=0 Q=0 R = 1 S = 1 : illegal

29. R S Q Q S-R Latch (Or S-R Flip-Flop) • Feedback is the key to memory/state elements. • Once a value is fed to the element, it circulates inside the element and renews itself, even after the input is turned off. • Other memory devices can be built from the basic latch. Illegal

30. Clock D Q Q S-R Flip-Flop With a Clock Clocked "D" Latch • This latch has one input, called "D". • When the clock is low, AND gates force zero on all inputs to the S-R latch  no change in state. • When clock is high, the value at D sets the "S" input of the latch; inverted D sets the "R" input of the latch.

31. D-Flip-Flop (1) • On each clock pulse the FF should be meaningful • Therefore the R and S lines should be opposite • If so do we still need both of them?

32. D Flip-Flop (2) • D Flip-Flop when the clock is pulsing:

33. Clock D Q Q D C Q t delay t delay t delay "D" Latch Clocking Waveforms The output "D" responds to the change in input, a characteristic delay after the clock goes high.

34. Q Q Q D D Latch D D Latch D Clock Q C C Edge Triggered "D" flip-flop The first latch is called the master, the second latch is called the slave • When the clock goes high, the first D latch (master) accepts the change in input • Because of the inverter, the change is blocked from moving on the second D latch (slave). • When the clock goes low, the slave latch accepts the change in input

35. Q0 Q1 Q2 Q(n-1) Q Q Q Q ET-D Latch ET-D Latch ET-D Latch ET-D Latch D D D D . . . C C C C Clock D0 D1 D2 D(n-1) Registers Registers can be built from a series of ET D latches connected to the same clock

36. State element 1 Combinational Logic State element 2 The Register File • Modern digital systems are based on logic with state variables, which are changed according to a clock. • The system consists of two types of logic -- combinational and sequential. • Combinational logic  a change in inputs directly causes a change in output, after a characteristic delay. Different from sequential logic which only changes on the clock. • Sequential logic contains state elements or memory elements. leading edge clock period leading edge The simplest type of clocking system to understand is built with edge triggered state elements. The diagram shows a system which clocks on the leading edge of the clock.

37. Register File 3 bits read reg 1 read reg 2 Implementation of double read port 32 bits MUX register 0 data 1 data 2 3 bits 32 bits 32 bits read data 1 read data 2 read reg 1 read reg 2 write reg write data register 1 32 bits 32 bits . . . 3 bits 32 bits register 6 3 bits 32 bits 32 bits register 7 32 bits 3 bits write enable MUX 1 bit 32 bits

38. Write Port Implementation write enable 1 bit 1 bit 1 bit n-to-1 decoder register 0 0 1 . . 6 7 C D Clock register 1 . . . 3 bits C D Reg # . . . C D C D register 6 register 7 C D write data 32 bits