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Efficient Embedding of Deterministic Test Data. Mudassar Majeed 1 , Daniel Ahlström 1 , Urban Ingelsson 1 , Gunnar Carlsson 2 and Erik Larsson 1. 1 Department of Computer and Information Science, Linköping University, Sweden. 2 Ericsson AB BU Networks SE-164 80 Stockholm Sweden. Purpose.
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Efficient Embedding of Deterministic Test Data Mudassar Majeed1, Daniel Ahlström1, Urban Ingelsson1, Gunnar Carlsson2 and Erik Larsson1 1Department of Computer and Information Science, Linköping University, Sweden 2Ericsson AB BU Networks SE-164 80 Stockholm Sweden
Purpose • Printed Circuit Boards (PCBs) include an increasing number of integrated circuits (ICs), often of the same type • Example: • Ericsson telecommunication systems contain PCBs with 36 ICs where 4 ICs are of type A, 8 ICs of type B, 8 ICs of type C and 16 ICs of type D • In-field testing is needed due to harsh environment • For in-field test, the problem is to deliver test data to the system • Straight forward solution is to store test data in the system • Drawbacks: • High memory requirements • Inflexibility in applying different tests • The proposed solution uses an embedded test controller to manipulate test data by exploiting structural information of the system • Benefits: Reduces memory requirements and provides flexibility Efficient Embedding of Deterministic Test Data
Outline • Introduction • Proposed Solution • Experiments and Results • Conclusions MARKERINGSYTA FÖR BILDER När du gör egna slides, placera bilder och andra illustrationer inom dessa fält. Titta gärna i ”baspresentationen” för exempel på hur placeringen kan göras.
Need for Remote System Test • Flexibility in applying commands • Embedded test solution Command 1: Test All Components Command 2: Test Only Component A Test Engineer at Office System at Remote Location Introduction
Embedded Test Solution Command 1: Test All Components Test Data Components Embedded Test Solution A B B Test Resp. Command 2: Test Only Component A PCB Introduction
A IEEE 1149.1 Standard ICs connected serially (IEEE 1149.1) B B • IEEE 1149.1 Standard for PCB testing • Supports testing core logic • Instructions INTEST, BYPASS Introduction
A IC Under Test Using IEEE 1149.1 Standard Test component A Bypass component A A 1 bit 4 bits BYPASS INTEST Stimuli: Instruction: INTEST A BYPASS A IEEE 1149.1 • IR-scan: Set instruction • DR-scan: Apply (execute) IR-scan defines the length of the 1149.1 chain Introduction
A A System Under Test Using IEEE 1149.1 Std. B B Command 1: Test All Components INTEST A INTEST B INTEST B Test Vectors B B Command 2: Test Only Component A INTEST A BYPASS B BYPASS B Introduction
Naive Embedded Test Controller Command 1: Test All Components (INTEST A INTEST B INTEST B) CPU Command 2: Test Only Component A (INTEST A BYPASS B BYPASS B) Memory Embedded Test Solution High memory requirements and inflexibility in applying the tests Introduction
Outline • Introduction • Proposed Solution • Experiments and Results • Conclusions MARKERINGSYTA FÖR BILDER När du gör egna slides, placera bilder och andra illustrationer inom dessa fält. Titta gärna i ”baspresentationen” för exempel på hur placeringen kan göras.
Key Idea Command 1: Test All Components INTEST A INTEST B INTEST B Command 2:Test Only Component A INTEST A BYPASS B BYPASS B 1 2 Structural Information Command 1: Type A 3 Concatenator Type B Command 2: Command Memory Embedded Test Solution Provides flexibility in applying the tests Proposed Solution
1. Memory Requirements Comparison Memory Memory Naive approach Proposed concatenation approach Reduces memory requirements Proposed Solution
A 2. Structural Information B B Structural Information - Types of components - Order of components in the system - Instruction Register Length - Data Register Length - Instructions Proposed Solution
A 3. Concatenator B B Steps for a given command: Read structural information Read component specific test stimuli Concatenate the stimuli Scan in instruction vector (if required) Scan in and apply test vector Scan out test response Compare with expected response If exit condition met, then terminate Else repeat step 2 Proposed Solution
Outline • Introduction • Proposed Solution • Experiments and Results • Conclusions MARKERINGSYTA FÖR BILDER När du gör egna slides, placera bilder och andra illustrationer inom dessa fält. Titta gärna i ”baspresentationen” för exempel på hur placeringen kan göras.
Objectives • To show that the approach works: • We used a PC as test controller and an FPGA as system under test • To see how memory requirements are reduced: • Naive Approach vs Proposed Concatenation Approach (for test command: “test all components”) • We created systems using industrial circuits as ICs % Reduction in Memory Requirements = Experiments and Results
Industrial Circuits Z. Wang and K. Chakrabarty. Test data compression for IP embedded cores using selective encoding of scan slices. In Proc. International Test Conference (ITC), pp. 581--590, 2005. Experiments and Results
Industrial Circuits ckt-1 ckt-2 ckt-3 ckt-4 ckt-5 ckt-6 ckt-7 ckt-8 Set # of Multiplications Design 2 1 3 20 2 3 2 20 2 3 8 20 Experiments and Results
Results Set 8 (ckt-8, 237.6 MBs) MBs Set 1 (ckt-1) Set 2 (ckt-2) Set 3 (ckt-3) Set 7 (ckt-7) Set 4 (ckt-4) Percentage Reduction in Memory Requirements Set 5 (ckt-5) Average Set 6 (ckt-6) Set 7 (ckt-7) Set 8 (ckt-8) Average Set 1 (ckt-1) Number of Multiplications Experiments and Results
Conclusions • Printed Circuit Boards (PCBs) include an increasing number of integrated circuits (ICs), often of the same type • Systems fail in operation and require in-field testing • Test data volume requires huge memory • The proposed solution exploits, • Structural Information of the system • The fact that multiple components of the same type require same test data • The test data manipulation via an embedded test controller • The reduction in memory requirements depends upon the number of components of the same type • Example: • Ericsson telecommunication systems contain PCBs with 36 ICs where 4 ICs are of type A, 8 ICs of type B, 8 ICs of type C and 16 ICs of type D
Efficient Embedding of Deterministic Test Data Mudassar Majeed1, Daniel Ahlström1, Urban Ingelsson1, Gunnar Carlsson2 and Erik Larsson1 1Department of Computer and Information Science, Linköping University, Sweden 2Ericsson AB BU Networks SE-164 80 Stockholm Sweden