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D rag and A tmospheric N eutral D ensity E xplorer (DANDE) C ommand and D ata H andling

D rag and A tmospheric N eutral D ensity E xplorer (DANDE) C ommand and D ata H andling (CDH) Critical Design Review October 11 th , 2007 Brandon Gilles (EE) James Gorman (ECE) Eric McIntyre (ECE) Gabriel Thatcher (EE). System Architecture Review. 2. Overview of Current Status.

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D rag and A tmospheric N eutral D ensity E xplorer (DANDE) C ommand and D ata H andling

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  1. Drag and Atmospheric NeutralDensity Explorer (DANDE) CommandandDataHandling (CDH) Critical Design Review October 11th, 2007 Brandon Gilles (EE) James Gorman (ECE) Eric McIntyre (ECE) Gabriel Thatcher (EE)

  2. System Architecture Review 2

  3. Overview of Current Status Completed ‘Meter-Stones’ • 8-bit board ordered. • New Linux Kernel running. • I2C driver compiled, loaded, and O-scope tested. • 32-bit board up and running with new Kernel. • Software Use Cases and Software Requirements (SRS) Specification • Fully defined • Approved by DANDE management.

  4. Overview of Current Status In the Works • 8-bit board assembly and test. • 8-bit software architecture. • Library support package • Bus-messaging driver • 32-bit software modeling • Architecture, Object, and Sequence Models Needs Attention • Watchdog Circuitry

  5. Hardware Subsystems

  6. Subsystem Schematics

  7. Subsystem Schematics

  8. Subsystem Board Overview

  9. Subsystem Board Overview

  10. Subsystem Board Visualization

  11. Subsystem Board Visualization

  12. Hardware Central Processor

  13. 32-bit Board • Build or Buy Decision: Buy • Atmel NGW100 Reference Design ~ $80

  14. Why? • Software Development Schedule • Man-hours desperately needed • Already hard-pressed to finish software • Cost-Benefit Analysis • NGW100 meets most requirements • Large development time and cost • Atmel needed 8-layers to implement NGW100 • 256-ping BGA package

  15. Software

  16. Software Development Cycle • Use-cases • Requirements Definitions • Requirements Approval • Architectural Support • Object Model • Sequence Model • Buildable Stub • Iterative Testing • Final Implementation • Completed – 9/15 • Completed – 9/24 • Completed – 10/1 • ~Completed • In Progress • In Progress • In Progress • Not Started • Not Started

  17. 32-bit Software Architecture

  18. Data Flows Science Data Housekeeping Data

  19. Subsystem Communication • I2C link to subsystems • Standardized Transmission Format across all subsystems • Communication done through Bus Messenger via IPC

  20. Boot-Up Sequence

  21. Project Goals

  22. Project Goals Milestone 1 Goals • Subsystem board and support code complete • Software analysis complete • Architecture Support • Object Model • Sequence Model • Stub of 32-bit software compiled Milestone 2 Goals • 32-bit Software • 80% functionality based on SRS • Test iteration 2 of 4 complete • 8-bit to 32-bit integration complete

  23. Project Goals Open-Lab Expo • 32-bit software • 100% functionality based on SRS • Test iteration 4 of 4 complete • 8-bit to 32-bit communication at 100% • Demo of Mach Satellite Operation • Central Processor • Two Subsystems • Intercommunication and Control

  24. Current Division of Labor • Brandon Gilles • Project Manager • REA - Linux Kernel • REA - 32-bit Hardware • James Gorman • REA - 8-bit Hardware and Software Reference Design • REA - Watch Dog and Long Dog Circuitry • Eric McIntyre • REA - 32-bit Software • Architecture • Analysis and Design • Implementation • Gabriel Thatcher • REA - Memory Voting Logic • REA - Subsystem Hardware Interfacing Time Permitting De-Scope • Across the board • 32-bit Software Analysis, Design and Implementation REA - Responsible Engineering Authority

  25. Backup Slides

  26. Parts List Overview What we have • 3 NGW100s • Central Processor Boards • 2 STK500s • Subsystem Programming Boards What we Need • 2 Subsystem Boards (arriving today) • Reference Design for subsystem Developers

  27. Detailed Parts List

  28. Schedule

  29. 32-bit Schematics

  30. 32-bit Schematics

  31. Exploded Satellite View

  32. Wiring Harness FOV360° FOV360° Acc Acc EPS EPS Photovoltaics 30W Photovoltaics 30W CDH CDH SFT SFT ACC ACC Acc Acc Acc Acc x4 x4 I2C I/O I2C I/O RAM TBD RAM TBD OS OS Battery A 14.4V 4AH Battery A 14.4V 4AH Battery B 14.4V 4AH Battery B 14.4V 4AH Inhibit Inhibit Scheduling Comm ADCS Science Scheduling Comm ADCS Science Control Control CPU AVR32 CPU AVR32 LV electrical interface LV electrical interface x4 x4 Acc Acc Acc Acc Inhibit Inhibit ABS ABS Serial I/O Serial I/O Regulation Regulation Control Control Acc Acc SSDTBD SSDTBD SEP SEP NMS NMS Instrument Instrument Mech1 Mech1 RTC RTC Instrument Instrument Lightband assy. Lightband assy. Control Control FOV32° x 1° FOV32° x 1° THM THM Coatings, Insulation Coatings, Insulation Mech2 Mech2 Control Control Sensors Sensors Control Control COM COM ADC ADC Torquerod A Torquerod A Tx Ant Tx Ant Tx 70cm 38.4kbps Tx 70cm 38.4kbps FOV90° FOV90° Control Control Torquerod A Torquerod A Instrument Instrument Mag (3-axis) Mag (3-axis) Satellite Sep Plane (SSP) Satellite Sep Plane (SSP) TNC TNC FOV 32° x 1° FOV 32° x 1° Rx 2m 9.6kbps Rx 2m 9.6kbps Rx Ant Rx Ant FOV90° FOV90° Horizon Crossing Sensor Horizon Crossing Sensor Horizon Crossing Sensor Horizon Crossing Sensor FOV 2° FOV 2° FOV 2° FOV 2° Functional Block Diagram 32

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