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HCAL Upgrade –Status and Prospects

HCAL Upgrade –Status and Prospects. Tariq Aziz TIFR, Mumbai. SINP, Kolkata, December 20, 2012. Efforts for HO-Upgrade -- LS1. SiPM Control Board. Assembly of hardware Setting up of QC station Software for fast & slow DAQ as well as QC data analysis. Set up at CRL, Ooty.

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HCAL Upgrade –Status and Prospects

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  1. HCAL Upgrade –Status and Prospects Tariq Aziz TIFR, Mumbai SINP, Kolkata, December 20, 2012

  2. Efforts for HO-Upgrade -- LS1 SiPM Control Board Assembly of hardware Setting up of QC station Software for fast & slow DAQ as well as QC data analysis

  3. Set up at CRL, Ooty

  4. Performance All tested components already at CERN Gearing up for Installation and Commissioning during LS1 -- 2013-14

  5. Opportunities for HB/HE Upgrade- LS2 Get involved in Fabrication & Testing of Front End Electronics Boards –under developments About 300 boards ( HB +HE) needed including spares The Charge (Q) Integrator and Encoder (QIE) Higher versions will incorporate TDC Importing QIE-10 or Higher version may be tricky

  6. The QIE10 is the latest device for fast, wide dynamic range, dead-timeless ADC’s that will also incorporate TDC information in the digital output Dynamic range of QIE10 is 3.2 fC to 340 pC (17-bit) New versions incorporate timing information for signal into output data TDC based on the rising edge of the pulse and discriminator level output For off-chip processing. An 8 bit programmable threshold will be used to set the Discriminator threshold. A TDC in QIE will convert the rising edge discriminated signal into 6-bit digital Output, providing a TDC with 500 ps bin The discriminator levels (rising and falling edges) will also be sent off the device to FPGA for additional pulse width determination Radiation hard & Compact low power device Each QIE card responsible for 24 channels of analog data Similar for HF, though PMT’s and not SiPM’s

  7. Intelligent response

  8. PCB making and mounting various components • Members from TIFR and SINP visited Mumbai and Bangalore • And identified firms that understand the complexity and could do the job that includes PCB (12 layer) and mounting various IC’s • Testing in the labs (at SINP and TIFR) for QC • Costs under discussion - should be mangeable

  9. Some remarks QIE based FEE is the state of the art Offers opportunities to learn advanced signal processing and data handling Members from SINP & TIFR have carried out initial tests and surveys for in-house fabrication and testing Most of the fabrication and assembly possible with local industries

  10. Backup

  11. Action items • Got Quotations for the 12 layer Board (the current Prototype Board close to the Final design) • Took Part in the Testing of the FPGA boards at SINP and the QIE P4 version board in the test-beam 2012 with useful experience • The final design of the FEE board expected in Feb 2013 along with new FPGA and maybe a Single Board instead of 2 boards.

  12. Front End Board for HCAL Upgrade • The FEE, front end electronics board for HE,HB and HF is Common . • The FEE consists of two boards which are evaluating since last test-beam. • One is a QIE8 (now QIE10) board and another one is a FPGA with SPF transducer board. • These two prototype boards were given to us by Prof Chris Tully.

  13. The QIE10 is the latest device for fast, wide dynamic range, dead-timeless ADC’s That will also incorporate TDC information in the digital output Should be radiation hard

  14. Home Work done • Studied in details the two boards given by Prof Chris ,with constant touch with the experts . • Understood the layout complexity and the functionality of the components on board. • The schematics, gerber files for PCB fabrication and other details obtained from the experts and with the help of our SINP colleagues.

  15. QIE8 Board details

  16. Conclusion • The cost of the PCB making alone will be roughly about Rs 40K • The assembly of the components will be approx Rs 60-70K . • The time taken for the Baord delivery after giving the gerber files per baord is about 4-5 weeks orso.

  17.   I had long discussion with Chris Tully when I was atCERN. He was very keen on me taking entire vertical slice starting from front-end to digital signalprocessing to DAQ with micro-TCA. What I think will be very challenging and doable is DSP using FPGAbased embedded system. Though he wanted me to carry all the existing hardware to get started; I told him that I will be very pleased to take this responsibility provided we develop human resources who can have desired expertise back home.    Essential it involves signal processing of digitizeddata from QIE10 electronics. Though I do not exact details but it will be similar to what will be achievedthrough DCC in present system. To put things in perspective, DCC's are heart of HCAL electronics. • The FEE consists of two boards which are evaluating since last test-beam. • One is a QIE8 (now QIE10) board and another one is a FPGA with SPF transducer board

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