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Microcontroller

Microcontroller. AT91SAM9261S. FEATURES. • Incorporates the ARM926EJ-S™ ARM Thumb Processor DSP Instruction Extensions ARM Jazelle Technology for Java Acceleration 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz

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Microcontroller

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  1. Microcontroller AT91SAM9261S

  2. FEATURES • Incorporates the ARM926EJ-S™ ARM Thumb Processor DSP Instruction Extensions ARM Jazelle Technology for Java Acceleration 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer 210 MIPS at 190 MHz Memory Management Unit • Additional Embedded Memories 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed

  3. • External Bus Interface (EBI) Supports SDRAM, Static Memory, NAND Flash and CompactFlash • USB 1-USB 2.0 Full Speed (12 Mbits per second) Host Double Port Dual On-chip Transceivers Integrated FIFOs and Dedicated DMA Channels 2-USB 2.0 Full Speed (12 Mbits per second) Device Port On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs

  4. • Clock Generator (CKGR) 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator and two PLL • Nineteen Peripheral DMA (PDC) Channels • Multimedia Card Interface (MCI) SDCard and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard complaint • Required Power Supplies: 1.08V to 1.32V for VDDCORE and VDDBU 3.0V to 3.6V for VDDOSC and for VDDPLL 2.7V to 3.6V for VDDIOP (Peripheral I/Os) 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)

  5. • Fully Featured System Controller (SYSC) for Efficient System Management including 1- Reset Controller, 2-Shutdown Controller, 3-Four 32-bit Battery Backup Registers 4-Power Management Controller (PMC) 5-Advanced Interrupt Controller (AIC) 6-Three 32-bit Parallel Input/Output Controllers 7- Three Synchronous Serial Controllers (SSC) 8-LCD Controller 9-Peripheral DMA Controller

  6. TIMERS • Periodic Interval Timer (PIT) 20-bit Interval Timer plus 12-bit Interval Counter • Watchdog Timer (WDT) Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock • Real-Time Timer (RTT) 32-bit Free-running Backup Counter Running at Slow Clock • One Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, Two multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

  7. Processor and Architecture • ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets 1-ARM High-performance 32-bit Instruction Set 2-Thumb High Code Density 16-bit Instruction Set • Standard ARM v4 and v5 Memory Management Unit (MMU) 1- Access Permission for Sections 2- Access Permission for large pages and small pages can be specified separately for each quarter of the page 3- 16 embedded domains

  8. • DSP Instruction Extensions • 5-Stage Pipeline Architecture • 16 Kbyte Data Cache, 16 Kbyte Instruction Cache 1- Virtually-addressed 4-way Associative Cache 2- Eight words per line 3- Write-through and Write-back Operation • Bus Interface Unit (BIU) 1-Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface 2-On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)

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