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MIPS Pipeline and Branch Prediction Implementation. Shuai Chang. Project Overview. ECE 369 Project Single Cycle Datapath Easy to implement Poor performance Performance Consideration Resource utilization Pipeline implementation Pipeline + Branch prediction. Original Design.
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MIPS Pipeline and Branch Prediction Implementation Shuai Chang
Project Overview • ECE 369 Project Single Cycle Datapath • Easy to implement • Poor performance • Performance Consideration • Resource utilization • Pipeline implementation • Pipeline + Branch prediction
Methodology • Implemented in Verilog HDL • Simulation • Xilinx ISE 13.2 • Hardware • Xilinx Spartan 3E FPGA Devlopment Board
Methodology • Implementation • Pipeline • Branch prediction
Methodology • Inputs • 2 files: Assembly Program and Data file 16 * 16 Window 32 * 32 Frame X = 0, Y = 8, SAD (Sum of Absolute Difference) = 0 is expected to be returned
Methodology • Outputs • Returned X, Y • SAD • Execution Time = CycleCount * CriticalPathDelay
Start Earlier? • Support more instructions • Optimize logic • Cache implementation