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PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs

PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs. Rohit Kumar Dr. Ann Gordon-Ross { kumar , ann }@ chrec.org Dept. of Electrical and Computer Engineering University of Florida, Gainesville , FL 32608 USA.

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PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs

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  1. PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs Rohit Kumar Dr. Ann Gordon-Ross {kumar, ann}@chrec.org Dept. of Electrical and Computer Engineering University of Florida, Gainesville, FL 32608 USA This work was supported in part by the I/UCRC program of the National Science Foundation under Grant Nos. EEC-0642422 and IIIP-1161022. Any opinions, finding, and conclusions or recommendations expressed in this material are of the author(s) and do not reflect views of the National Science Foundation.

  2. PR Modeling Language and Application Partitioning PRML flow Designer selects a PR architecture for implementation from Pareto optimal set based on system goals PR architecture evaluation with FoRSE User-created PRML model Partitioning and PR architecture generation *Formulation-level Design Space Exploration for Partially Reconfigurable FPGAs. R. Kumar and A. Gordon-Ross. International Conference on Field-Programmable Technology (FPT), December 2011. • Partial reconfiguration (PR) benefits: • Enhanced hardware resource time-multiplexing via isolated reconfiguration • Area and power savings • Leveraging these benefits is challenging! • Early PR benefit evaluation alleviates design time efforts • Early decisions prune design space • Algorithm-level application modeling and partitioning requires nominal effort • PR modeling language (PRML) • Application-behavior-independent graph-theoretic technique for PR partitioning and benefit analysis • Partitioning rules create all PR architectures • FoRSE* tool generates Pareto optimal PR architecture set trading off designer-specified constraints • Reduced design exploration time • Designers only consider Pareto optimal set

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