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Boolean Algebra and Digital Logic: Truth Tables, Gates, Circuits, and Flip-Flops

Learn about Boolean algebra, truth tables, logic gates, circuits, and flip-flops in digital logic. Gain an understanding of how these concepts are used to design and analyze digital systems.

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Boolean Algebra and Digital Logic: Truth Tables, Gates, Circuits, and Flip-Flops

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  1. Chapter 3 Boolean Algebra and Digital Logic Linda Null, Julia Lobur

  2. Figure 03.UN01: "I've always loved that word, Boolean." Claude Shannon

  3. Table 03.T01: Truth Table for AND -

  4. Table 03.T02: Truth Table for OR -

  5. Table 03.T03: Truth Table for NOT -

  6. Table 03.T04: The Truth Table for F(x,y,z) = x + y′z -

  7. Table 03.T05: Basic Identities of Boolean Algebra -

  8. Table 03.T06: Truth Table for the AND Form of DeMorgan's Law -

  9. Table 03.T07: Truth Table Representation for a Function and Its Complement -

  10. Table 03.T08: Truth Table Representation for the Majority Function -

  11. Figure 03.F01: The Three Basic Gates -

  12. Figure 03.F02: a) The Truth Table for XOR b) The Logic Symbol for XOR -

  13. Figure 03.F03: Truth Table and Logic Symbols for NAND -

  14. Figure 03.F04: Truth Table and Logic Symbols for NOR -

  15. Figure 03.F05: Three Circuits Constructed Using Only NAND Gates -

  16. Figure 03.F06: A Three-Input OR Gate Representing x + y + z -

  17. Figure 03.F07: A Three-Input AND Gate Representing x yz -

  18. Figure 03.F08: AND Gate with Two Inputs and Two Outputs -

  19. Figure 03.F09: Logic Diagram for F(x, y, z) = x + y'z -

  20. Figure 03.UN02: Line drawing showing a circuit. -

  21. Figure 03.F10: Simple SSI Integrated Circuit -

  22. Figure 03.UN08: Line drawing showing a function that evaluates to one AND gate using x and y as input. -

  23. Table 03.T09: Truth Table for a Half-Adder -

  24. Figure 03.F11: Logic Diagram for a Half-Adder -

  25. Figure 03.F12: a) Truth Table for a Full-Adder b) Logic Diagram for a Full-Adder -

  26. Figure 03.F13: Logic Diagram for a Ripple-Carry Adder -

  27. Figure 03.F14: a) A Look Inside a Decoder b) A Decoder Symbol -

  28. Figure 03.F15: a) A Look Inside a Multiplexer b) A Multiplexer Symbol -

  29. Table 03.T10: Parity Generator -

  30. Table 03.T11: Parity Checker -

  31. Figure 03.F16: 4-Bit Shifter -

  32. Figure 03.F17: A Simple Two-Bit ALU -

  33. Figure 03.F18: A Clock Signal Indicating Discrete Instances of Time -

  34. Figure 03.F19: Example of Simple Feedback -

  35. Figure 03.F20: SR Flip-Flop Logic Diagram -

  36. Figure 03.F21: a) SR Flip-Flop b) Clocked SR Flip-Flop c) Characteristic Table for the SR Flip-Flop d) Timing Diagram for the SR Flip-Flop (assuming initial state of Q is 0) -

  37. Table 03.T12: Truth Table for SR Flip-Flop -

  38. Figure 03.F22: a) JK Flip-Flop b) JK Characteristic Table c) JK Flip-Flop as a Modified SR Flip-Flop d) Timing Diagram for JK Flip-Flop (assuming initial state of Q is 0) -

  39. Figure 03.F23: a) D Flip-Flop b) D Flip-Flop Characteristic Table c) D Flip-Flop as a Modified SR Flip-Flop d) Timing Diagram for D Flip-Flop -

  40. Figure 03.F24: JK Flip-Flop Represented as a Moore Machine -

  41. Figure 03.F25: Simplified Moore Machine for the JK Flip-Flop -

  42. Figure 03.F26: JK Flip-Flop Represented as a Mealy Machine -

  43. Figure 03.F27: a) Block Diagram for Moore Machines b) Block Diagram for Mealy Machines -

  44. Figure 03.F28: Components of an Algorithmic State Machine -

  45. Figure 03.F29: Algorithmic State Machine for a Microwave Oven -

  46. Figure 03.UN02: Finite State Machine for Accepting a Variable Name -

  47. Figure 03.F30: a) 4-Bit Register b) Block Diagram for a 4-Bit Register -

  48. Figure 03.F31: 4-Bit Synchronous Counter Using JK Flip-Flops -

  49. Figure 03.F32: 4 x 3 Memory -

  50. Figure 03.F33: Convolutional Encoder for PRML -

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