ARM Microprocessors

1. ARM Microprocessors

2. Content • The ARM processor • ARM instruction set • Summary

3. The ARM processor

4. ARM Ltd • ARM was originally developed at Acron Computer Limited, of Cambridge, England between 1983 and 1985. • 1980, RISC concept at Stanford and Berkeley universities. • First RISC processor for commercial use • 1990 Nov, ARM Ltd was founded • ARM cores • Licensed to partners who fabricate and sell to customers. • Technologies assist to design in the ARM application • Software tools, boards, debug hardware, application software, bus architectures, peripherals etc… • Modification of the acronym expansion to Advanced RISC Machine.

5. ARM Ltd Design and license ARM core design but not fabricate

6. Why ARM? • One of the most licensed and thus widespread processor cores in the world • Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras • Used especially in portable devices due to its low power consumption and reasonable performance

7. ARM processors • A simple but powerful design • A whole family of designs sharing similar design principles and a common instruction set

8. ARM powered products

9. Naming ARM • ARMxyzTDMIEJFS • x: series • y: MMU • z: cache • T: Thumb • D: debugger • M: Multiplier • I: EmbeddedICE (built-in debugger hardware) • E: Enhanced instruction • J: Jazelle (JVM) • F: Floating-point • S: Synthesizible version (source code version for EDA tools)

12. ARM 7 applications

13. ARM9 applications

14. ARM11 applications

15. ARM CortexM applications • Dell E4300 Latitude Laptop • instant boot-up for users and access to select applications, with multi-day battery lifetimes

16. ARM CortexA applications

17. ARM CortexR

18. Popular ARM architectures (selection) • ARM7TDMI • 3 pipeline stages (fetch/decode/execute) • High code density/low power consumption • One of the most used ARM-version (for low-end systems) • All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI • Compatible with ARM7 • 5 stages (fetch/decode/execute/memory/write) • Separate instruction and data cache • ARM11

19. ARM design philosophy • Small processor for lower power consumption (for embedded system) • High code density for limited memory and physical size restrictions • The ability to use slow and low-cost memory • Reduced die size for reducing manufacture cost and accommodating more peripherals

20. ARM architecture

21. ARM architecture • Load/store architecture • A large array of uniform registers • Fixed-length 32-bit instructions • 3-address instructions

22. RISC Architecture • Berkeley incorporated a Reduced Instruction Set Computer (RISC) architecture. • It has the following key features: • A fixed (32-bit) instruction size with few formats; • CISC processors typically had variable length instruction sets with many formats. • A load–store architecture where instructions that process data operate only on registers and are separate from instructions that access memory; • CISC processors typically allowed values in memory to be used as operands in data processing instructions. • A large register bank of thirty-two 32-bit registers, all of which could be used for any purpose, to allow the load-store architecture to operate efficiently; • CISC register sets were getting larger, but none was this large and most had different registers for different purposes

23. RISC Organization • Hard-wired instruction decode logic • CISC processor used large microcode ROMs to decode their instructions • Pipelined execution • CISC processors allowed little, if any, overlap between consecutive instructions (though they do now) • Single-cycle execution • CISC processors typically took many clock cycles to completes a single instruction → Simple is beauty Compiler plays an important role

24. ARM Architecture vs. Berkeley RISC • Features used • Load/Store architecture • Fixed-length 32-bit instructions • 3-address instruction formats ADD d, S1, S2 ; d := S1 + S2 • Features rejected • Register windows → costly • Use shadow (banked) registers in ARM • Delay branch • Badly with branch prediction • Single-cycle execution of all instructions • Most single cycle, many other take multiple clock cycles

25. ARM features • Different from pure RISC in several ways: • Variable cycle execution for certain instructions: multiple-register load/store (faster/higher code density) • Inline barrel shifter leading to more complex instructions: improves performance and code density • Thumb 16-bit instruction set: 30% code density improvement • Conditional execution: improve performance and code density by reducing branch • Enhanced instructions: DSP instructions

26. Data Size and Instruction Set • ARM processor is a 32-bit architecture • When used in relation to the ARM • Byte means 8 bits • Halfword means 16 bits (two bytes) • Word means 32 bits (four bytes) • Most ARM’s implement two instruction sets • 32-bit ARM instruction set • 16-bit Thumb instruction set

27. Data Types • ARM processor supports 6 data types • 8-bits signed and unsigned bytes • 16-bits signed and unsigned half-word, aligned on 2-byte boundaries • 32-bits signed and unsigned words, aligned on 4-byte boundaries • ARM instructions are all 32-bit words, word-aligned • Thumb instructions are half-words, aligned on 2-byte boundaries

28. Processor Modes • The ARM has seven basic operating modes • User: unprivileged mode under which most tasks run • FIQ: entered when a high priority (fast) interrupts is raised • IRQ: entered when a low priority (normal) interrupts is raised • Supervisor: entered on reset and when a software interrupt instruction is executed • Abort: used to handle memory access violations • Undefined: used to handle undefined instructions • System: privileged mode using the same registers as user mode • Not in ARM architecture 1, 2, or 3

29. Processor Modes (cont.) • Exception modes • FIQ, IRQ, Supervisor, Abort, and Undefined • Privileged modes • FIQ, IRQ, Supervisor, Abort, Undefined, and System

30. The Mode Bits • Mode changes by software control or external interrupts • Current program status register, CPSR

31. The Registers • ARM has 37 registers, all of which are 32 bits long • 1 dedicated program counter • 1 dedicated current program status register • 5 dedicated saved program status registers • 31 general purpose registers • The current processor mode governs which bank is accessible • Each mode can access • A particular set of r0 – r12 registers • A particular r13 (stack pointer, SP) and r14 (link register, LR) • The program counter, r15 (PC) • The current program status register, CPSR • Privileged modes (except system) can access • A particular SPSR (Saved Program Status Register)

32. r0 usable in user mode r1 r2 r3 exception modes only r4 r5 r6 r7 r8_fiq r8 r9_fiq r9 r10_fiq r10 r1 1_fiq r1 1 r13_und r12_fiq r13_irq r12 r13_abt r13_svc r14_und r13_fiq r14_irq r13 r14_abt r14_svc r14_fiq r14 r15 (PC) SPSR_und SPSR_irq SPSR_abt CPSR SPSR_svc SPSR_fiq system mode svc abort irq undefi ned fiq user mode mode mode mode mode mode Register Banking

33. General Purpose Registers • The unbanked registers • r0 – r15 • user and system mode refer to the same physical registers • The banked registers • r8_fiq – r12_fiq, r13_<mode>, and r14_<mode> • The set of physical registers depend on the processor mode • r13 is normally used as the stack pointer (SP) • r14 is also known as the link register (LR), which is used to store the return address from a subroutine • Register 15, PC • r15 is the program counter

34. Program Counter (r15) • When the processor is executing in ARM state: • All instructions are 32 bits wide • All instructions must be word-aligned • Therefore the PC value is stored in bits [32:2] with bits [1:0] undefined (as instruction cannot be halfword) • When the processor is executing in Thumb state: • All instructions are 16 bits wide • All instructions must be halfword-aligned • Therefore the PC value is stored in bits [32:1] with bits [0] undefined (as instruction cannot be byte-aligned)

35. Condition code flags N: Negative result form ALU Z: Zero result from ALU C: ALU Operation Carried out V: ALU operation oVerflowed Sticky overflow flag – Q flag Architecture 5TE only Indicates if saturation has occurred during certain operations Interrupt disable bits I = 1, disable the IRQ F = 1, disable the FIQ T Bit Architecture xT only T = 0, processor in ARM state T = 1, processor in Thumb state Mode bits Specify the processor mode Current Program Status Registers (CPSR)

36. Saved Program Status Register (SPSR) • Each privileged mode (except system mode) has associated with it a SPSR • This SPSR is used to save the state of CPSR when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed • Often the SPSR may be untouched from the time the privileged mode is entered to the time it is used to restore the CPSR • If the privileged supervisor calls to itself the SPSR must be copied into a general register and saved

37. Exceptions • Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults, also cover software interrupts, undefined instructiontraps, and the system reset • Three groups: • Exceptions generated as the direct effect of executing an instruction • Software interrupts, undefined instructions, and prefetch abort • Exceptions generated as a side effect of an instruction • Data aborts • Exceptions generated externally • Reset, IRQ and FIQ

38. Exception Entry (1/2) • When an exception arises • ARM completes the current instruction as best it can (except that reset exception) • handle the exception which starts from a specific location (exception vector). • Processor performs the following sequence: • Change to the operating mode corresponding to the particular exception • Stores the return address in LR_<mode> • Copy old CPSR into SPSR_<mode> • Set appropriate CPSR bits • If core currently in Thumb state then ARM state is entered. • Disable IRQs by setting bit 7 • If the exception is a fast interrupt, disable further faster interrupt by setting bit 6 of the CPSR

39. Exception Entry (2/2) • Force PC to relevant vector address • Normally the vector address contains a branch to the relevant routine • Exception handler use r13_<mode> and r14_<mode> to hold the stack point and return address

40. Exception Return • Once the exception has been handled, the user task is normally resumed • The sequence is • Any modified user registers must be restored from the handler’s stack • CPSR must be restored from the appropriate SPSR • PC must be changed back to the relevant instruction address • The last two steps happen atomically as part of a single instruction

41. Memory Organization • Word, half-word alignment (xxxx00 or xxxxx0) • ARM can be set up to access data in either little-endian or big-endian format, through they default to little-endian.

42. Features of the ARM Instruction Set • Load-store architecture • Process values which are in registers • Load, store instructions for memory data accesses • 3-address data processing instructions • Conditional execution of every instruction • Load and store multiple registers • Shift, ALU operation in a single instruction • Open instruction set extension through the coprocessor instruction • Very dense 16-bit compressed instruction set (Thumb)

43. Coprocessors • Up to 16 coprocessors can be defined • Expands the ARM instruction set • Each coprocessor can have up to 16 private registers of any reasonable size • Load-store architecture

44. Thumb • Thumb is a 16-bit instruction set • Optimized for code density from C code • Improved performance form narrow memory • Subset of the functionality of the ARM instruction set • Core has two execution states – ARM and Thumb • Switch between them using BX instruction • Thumb has characteristic features: • Most Thumb instructions are executed unconditionally • Many Thumb data process instruction use a 2-address format • Thumb instruction formats are less regular than ARM instruction formats, as a result of the dense encoding.

45. I/O System • ARM handles input/output peripherals as memory-mappedwith interrupt support • Internal registers in I/O devices as addressable locations with ARM’s memory map read and written using load-store instructions • Interrupt by normal interrupt (IRQ) or fast interrupt (FIQ) • Interrupt input signals are level-sensitive and maskable • May include Direct Memory Access (DMA) hardware

46. ARM instruction set

47. ARM assembly language program • ARM development board or ARM emulator • ARM instruction set • Standard ARM instruction set • A compressed form of the instruction set, a subset of the full ARM instruction set is encoded into 16-bit instructions – Thumb instruction • Some ARM cores support instruction set extensions to enhance signal processing capabilities

48. Instructions • Data processing instructions • Data transfer instructions • Control flow instructions

49. Conditional Execution • Most instruction sets only allow branches to be executed conditionally. • However by reusing the condition evaluation hardware, ARM effectively increase number of instruction • All instructions contain a condition field which determines whether the CPU will execute them • Non-executed instruction still take up 1 cycle • To allow other stages in the pipeline to complete • This reduces the number of branches which would stall the pipeline • Allows very dense in-line code • The time penalty of not executing several conditional instructions is frequently less than overhead of the branch or instruction call that would otherwise be needed

50. 31 28 27 0 cond Condition code