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CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH

CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH. Lecture 6 – ALU Design II: Multiply, Divide, and Floating Point Operations. Instructor: Prof. Jason Cong <cong@cs.ucla.edu>. B. 32. Review: ALU Design. Bit-slice plus extra on the two ends

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CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH

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  1. CS151BComputer Systems ArchitectureWinter 2002 TuTh 2-4pm - 2444 BH Lecture 6 – ALU Design II: Multiply, Divide, and Floating Point Operations Instructor: Prof. Jason Cong <cong@cs.ucla.edu>

  2. B 32 Review: ALU Design • Bit-slice plus extra on the two ends • Overflow means number too large for the representation • Carry-look ahead and other adder tricks 32 A signed-arith and cin xor co a0 b0 a31 b31 4 ALU0 ALU31 M co cin co cin s0 s31 C/L to produce select, comp, c-in Ovflw 32 S Jason Cong

  3. Review: Elements of the Design Process • Divide and Conquer (e.g., ALU) • Formulate a solution in terms of simpler components. • Design each of the components (subproblems) • Generate and Test (e.g., ALU) • Given a collection of building blocks, look for ways of putting them together that meets requirement • Successive Refinement (e.g., multiplier, divider) • Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings. • Formulate High-Level Alternatives (e.g., shifter) • Articulate many strategies to "keep in mind" while pursuing any one approach. • Work on the Things you Know How to Do • The unknown will become “obvious” as you make progress. Jason Cong

  4. Review: Summary of the Design Process Hierarchical Design to manage complexity Top Down vs. Bottom Up vs. Successive Refinement Importance of Design Representations: Block Diagrams Decomposition into Bit Slices Truth Tables, K-Maps Circuit Diagrams Other Descriptions: state diagrams, timing diagrams, reg xfer, . . . Optimization Criteria: Gate Count [Package Count] top down bottom up Area Logic Levels Fan-in/Fan-out Delay Power Pin Out Cost Design time Jason Cong

  5. MIPS arithmetic instructions • Instruction Example Meaning Comments • add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible • subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible • add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible • add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions • subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions • add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions • multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product • multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product • divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder • Hi = $2 mod $3 • divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder • Hi = $2 mod $3 • Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi • Move from Lo mflo $1 $1 = Lo Used to get copy of Lo Jason Cong

  6. MULTIPLY (unsigned) • Paper and pencil example (unsigned): Multiplicand 1000Multiplier 1001 1000 0000 0000 1000 Product 01001000 • m bits x n bits = m+n bit product • Binary makes it easy: • 0 => place 0 ( 0 x multiplicand) • 1 => place a copy ( 1 x multiplicand) • 4 versions of multiply hardware & algorithm: • successive refinement Jason Cong

  7. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 Unsigned Combinational Multiplier • Stage i accumulates A * 2 i if Bi == 1 • Q: How much hardware for 32 bit multiplier? Critical path? Jason Cong

  8. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 How does it work? 0 0 0 0 0 0 0 B0 • at each stage shift A left ( x 2) • use next bit of B to determine whether to add in shifted multiplicand • accumulate 2n bit partial product at each stage B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0 Jason Cong

  9. Unisigned shift-add multiplier (version 1) • 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Shift Left Multiplicand 64 bits Multiplier Shift Right 64-bit ALU 32 bits Write Product Control 64 bits Multiplier = datapath + control Jason Cong

  10. 1. Test Multiplier0 Multiply Algorithm Version 1 Start Multiplier0 = 1 Multiplier0 = 0 • Product Multiplier Multiplicand 0000 0000 0011 0000 0010 • 0000 0010 0001 0000 0100 • 0000 0110 0000 0000 1000 • 0000 0110 1a. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Jason Cong

  11. Observations on Multiply Version 1 • 1 clock per cycle =>  100 clocks per multiply • Ratio of multiply to add 5:1 to 100:1 • 1/2 bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in left of multiplicand as shifted=> least significant bits of product never changed once formed • Instead of shifting multiplicand to left, shift product to right? Jason Cong

  12. MULTIPLY HARDWARE Version 2 • 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 32 bits Multiplier Shift Right 32-bit ALU 32 bits Shift Right Product Control Write 64 bits Jason Cong

  13. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 How to think of this? Remember original combinational multiplier: Jason Cong

  14. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 Simply warp to let product move right... 0 0 0 0 • Multiplicand stay’s still and product moves right B0 B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0 Jason Cong

  15. Start Multiplier0 = 1 Multiplier0 = 0 1. Test Multiplier0 1a. Add multiplicand to the left half ofproduct & place the result in the left half ofProduct register 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Multiply Algorithm Version 2 Product Multiplier Multiplicand 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010 1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 Jason Cong

  16. Start Multiplier0 = 1 Multiplier0 = 0 1. Test Multiplier0 1a. Add multiplicand to the left half ofproduct & place the result in the left half ofProduct register 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Still more wasted space! Product Multiplier Multiplicand 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 00000001 0010 1: 0011 00000001 0010 2: 0001 1000 0001 0010 3: 0001 10000000 0010 1: 0001 10000000 0010 2: 0000 11000000 0010 3: 0000 11000000 0010 1: 0000 11000000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 Jason Cong

  17. Observations on Multiply Version 2 • Product register wastes space that exactly matches size of multiplier=> combine Multiplier register and Product register Jason Cong

  18. MULTIPLY HARDWARE Version 3 • 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Multiplicand 32 bits 32-bit ALU Shift Right Product (Multiplier) Control Write 64 bits Jason Cong

  19. 1. Test Product0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Multiply Algorithm Version 3 Start Product0 = 1 Product0 = 0 Multiplicand Product0010 0000 0011 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done Jason Cong

  20. Observations on Multiply Version 3 • 2 steps per bit because Multiplier & Product combined • MIPS registers Hi and Lo are left and right half of Product • Gives us MIPS instruction MultU • How can you make it faster? • What about signed multiplication? • easiest solution is to make both positive & remember whether tocomplement product when done (leave out the sign bit, run for 31 steps) • apply definition of 2’s complement • need to sign-extend partial products and subtract at the end • Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles • can handle multiple bits at a time Jason Cong

  21. Motivation for Booth’s Algorithm • Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0010 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 • ALU with add or subtract gets same result in more than one way: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 • For example • 0010 x 0110 0000 shift (0 in multiplier) – 0010 sub (first 1 in multpl.) . 0000 shift (mid string of 1s) . + 0010 add (prior step had last 1) 00001100 Jason Cong

  22. –1 + 10000 01111 Booth’s Algorithm middle of run end of run beginning of run 0 1 1 1 1 0 Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift was faster than add) • Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one Jason Cong

  23. Booths Example (2 x 7) Operation Multiplicand Product next? 0. initial value 0010 0000 01110 10 -> sub 1a. P = P - m 1110 + 1110 1110 01110 shift P (sign ext) 1b. 0010 1111 00111 11 -> nop, shift 2. 0010 1111 10011 11 -> nop, shift 3. 0010 1111 11001 01 -> add 4a. 0010 + 0010 0001 11001 shift 4b. 0010 0000 1110 0 done Jason Cong

  24. Booths Example (2 x -3) Operation Multiplicand Product next? 0. initial value 0010 0000 11010 10 -> sub 1a. P = P - m 1110 + 1110 1110 11010 shift P (sign ext) 1b. 0010 1111 01101 01 -> add + 0010 2a. 0001 01101 shift P 2b. 0010 0000 10110 10 -> sub + 1110 3a. 0010 1110 10110 shift 3b. 0010 1111 0101 1 11 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 10101 done Jason Cong

  25. MIPS logical instructions • Instruction Example Meaning Comment • and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND • or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR • xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR • nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR • and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant • or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant • xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant • shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant • shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant • shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) • shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable • shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable • shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable Jason Cong

  26. Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend "0" msb lsb "0" msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted! Jason Cong

  27. 1 0 S2 S1 S0 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 Combinational Shifter from MUXes B A Basic Building Block sel • What comes in the MSBs? • How many levels for 32-bit shifter? D 8-bit right shifter Jason Cong

  28. Barrel Shifter (2) • 2N-1 inputs (diagonal) • N outputs (horizontal) • N control signals (vertical) – only one can be true • Example – 2-bit right logical shift • SR2=1 • A0-A3: inputs • A4 = A5 = 1 Jason Cong

  29. Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend–1000 10 101 1010 –1000 10 Remainder (or Modulo result) See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor Dividend = Quotient x Divisor + Remainder=> | Dividend | = | Quotient | + | Divisor | 3 versions of divide, successive refinement Jason Cong

  30. DIVIDE HARDWARE Version 1 • 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Shift Right Divisor 64 bits Quotient Shift Left 64-bit ALU 32 bits Write Remainder Control 64 bits Jason Cong

  31. Start: Place Dividend in Remainder 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3. Shift the Divisor register right1 bit. n+1 repetition? Done Divide Algorithm Version 1 • Takes n+1 steps for n-bit Quotient & Rem. Remainder Quotient Divisor0000 01110000 0010 0000 Remainder < 0 Test Remainder Remainder  0 No: < n+1 repetitions Yes: n+1 repetitions (n = 4 here) Jason Cong

  32. Divide Algorithm I example (7 / 2) Remainder Quotient Divisor0000 0111 00000 0010 0000 1:1110 011100000 0010 0000 2:0000 011100000 0010 0000 3:0000 0111000000001 0000 1:1111 011100000 0001 0000 2:0000 011100000 0001 0000 3:0000 0111000000000 1000 1:1111111100000 0000 1000 2:0000 011100000 0000 1000 3:0000 0111000000000 0100 1:0000 001100000 0000 0100 2:0000 001100001 0000 0100 3:0000 001100001 0000 0010 1:0000 000100001 0000 0010 2:0000 000100011 0000 0010 3:0000 000100011 0000 0010 Answer: Quotient = 3 Remainder = 1 Jason Cong

  33. Observations on Divide Version 1 • 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted • Instead of shifting divisor to right, shift remainder to left? • 1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration Jason Cong

  34. Divide Algorithm I example: wasted space Remainder Quotient Divisor0000 0111 00000 0010 0000 1:1110 011100000 0010 0000 2:0000 011100000 0010 0000 3:0000 011100000 0001 0000 1:1111 011100000 0001 0000 2:0000 011100000 0001 0000 3:0000 011100000 0000 1000 1:1111 111100000 0000 1000 2:0000 011100000 0000 1000 3:0000 011100000 0000 0100 1:0000 001100000 0000 0100 2:0000 001100001 0000 0100 3:0000 001100001 0000 0010 1:0000 000100001 0000 0010 2:0000 000100011 0000 0010 3:0000 000100011 0000 0010 Jason Cong

  35. Divide: Paper & Pencil 01010 Quotient Divisor 0001 00001010 Dividend 00001–0001 0000 0001–0001 0 00 Remainder (or Modulo result) • Noticethat there is no way to get a 1 in leading digit!(this would be an overflow, since quotient would haven+1 bits) Jason Cong

  36. DIVIDE HARDWARE Version 2 • 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Divisor 32 bits Quotient Shift Left 32-bit ALU 32 bits Shift Left Remainder Control Write 64 bits Jason Cong

  37. Start: Place Dividend in Remainder 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. 3a. Shift the Quotient register to the left setting the new rightmost bit to 1. nth repetition? Done Divide Algorithm Version 2 Remainder Quotient Divisor 0000 01110000 0010 Remainder  0 Test Remainder Remainder < 0 No: < n repetitions Yes: n repetitions (n = 4 here) Jason Cong

  38. Observations on Divide Version 2 • Eliminate Quotient register by combining with Remainder as shifted left • Start by shifting the Remainder left as before. • Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half • The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many. • Thus the final correction step must shift back only the remainder in the left half of the register Jason Cong

  39. DIVIDE HARDWARE Version 3 • 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg) Divisor 32 bits 32-bit ALU “HI” “LO” Shift Left (Quotient) Remainder Control Write 64 bits Jason Cong

  40. Start: Place Dividend in Remainder 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. 3a. Shift the Remainder register to the left setting the new rightmost bit to 1. nth repetition? Done. Shift left half of Remainder right 1 bit. Divide Algorithm Version 3 Remainder Divisor0000 0111 0010 Test Remainder Remainder < 0 Remainder  0 No: < n repetitions Yes: n repetitions (n = 4 here) Jason Cong

  41. Observations on Divide Version 3 • Same Hardware as Multiply: just need ALU to add or subtract, and 64-bit register to shift left or shift right • Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide • Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary • Note: Dividend and Remainder must have same sign • Note: Quotient negated if Divisor sign & Dividend sign disagreee.g., –7 ÷ 2 = –3, remainder = –1 • What about? –7 ÷ 2 = –4, remainder = +1 • Possible for quotient to be too large: if divide 64-bit integer by 1, quotient is 64 bits (“called saturation”) Jason Cong

  42. What is in a number? • What can be represented in N bits? • Unsigned 0 to 2N - 1 • 2s Complement - 2N-1 to 2N-1 - 1 • 1s Complement -2N-1+1 to 2N-1-1 • Excess M 2 -M to 2 N - M - 1 • (E = e + M) • BCD 0 to 10N/4 - 1 • But, what about? • very large numbers? 9,349,398,989,787,762,244,859,087,678 • very small number? 0.0000000000000000000000045691 • rationals 2/3 • irrationals • transcendentals e,  Jason Cong

  43. Recall Scientific Notation exponent decimal point Sign, magnitude • Issues: • Arithmetic (+, -, *, / ) • Representation, Normal form • Range and Precision • Rounding • Exceptions (e.g., divide by zero, overflow, underflow) • Errors • Properties ( negation, inversion, if A  B then A - B  0 ) 23 -24 6.02 x 10 1.673 x 10 radix (base) Mantissa Sign, magnitude e - 127 IEEE F.P. ± 1.M x 2 Jason Cong

  44. Review from Prerequisties: Floating-Point Arithmetic Representation of floating point numbers in IEEE 754 standard: single precision 1 8 23 S E sign M mantissa: sign + magnitude, normalized binary significand w/ hidden integer bit: 1.M exponent: excess 127 binary integer actual exponent is e = E - 127 0 < E < 255 S E-127 N = (-1) 2 (1.M) 0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0 Magnitude of numbers that can be represented is in the range: -126 127 -23 ) 2 (1.0) (2 - 2 to 2 which is approximately: -38 38 to 3.40 x 10 1.8 x 10 (integer comparison valid on IEEE Fl.Pt. numbers of same sign!) Jason Cong

  45. Basic Addition Algorithm/Multiply issues For addition (or subtraction) this translates into the following steps: (1) compute Ye - Xe (getting ready to align binary point) (2) right shift Xm that many positions to form Xm 2 (3) compute Xm 2 + Ym if representation demands normalization, then normalization step follows: (4) left shift result, decrement result exponent (e.g., 0.001xx…) right shift result, increment result exponent (e.g., 101.1xx…) continue until MSB of data is 1 (NOTE: Hidden bit in IEEE Standard) (5) for multiply, doubly biased exponent must be corrected: Xe = 7 Ye = -3 Excess 8 extra subtraction step of the bias amount (6) if result is 0 mantissa, may need to zero exponent by special step Xe-Ye Xe-Ye = 7 + 8 = -3 + 8 4 + 8 + 8 Xe = 1111 Ye = 0101 10100 = 15 = 5 20 Jason Cong

  46. Extra Bits for Rounding "Floating Point numbers are like piles of sand; every time you move one you lose a little sand, but you pick up a little dirt." How many extra bits? IEEE: As if computed the result exactly and rounded. • Guard Digits: digits to the right of the first p digits of significand to guard against loss of digits – can later be shifted left into first P places during normalization. • IEEE 754 keeps 2 extra bits: guard bit and round bit Need of extra bits: For addition: 1.xxxxx 1.xxxxx 1.xxxxx + 1.xxxxx 0.001xxxxx 0.01xxxxx 1x.xxxxy 1.xxxxxyyy 1x.xxxxyyy Needed: post-normalization pre-normalization pre and post Jason Cong

  47. Rouding with Guard Digits Example: 2.56x100 + 2.34x102 (assuming 3 significant digits) With guard digits Without guard digits 2.3400 2.34 + 0.0256 + 0.02 -------------------- ------------- 2.3656 2.36 Rounded to 2.37 • one round digit must be carried to the right of the guard digit so that after a normalizing left shift, the result can be rounded, according to the value of the round digit • ulp: units in the last place • IEEE 754 guarantees the accuracy within one-half ulp Jason Cong

  48. Sticky Bit Additional bit to the right of the round digit to better fine tune rounding d0 . d1 d2 d3 . . . dp-1 0 0 0 0 . 0 0 X . . . X X X S X X S Sticky bit: set to 1 if exist any 1 bit fall off the end of the round digit + • Allow machine to see difference between 0.50…00 vs 0.50…01 • May set during addition when shifting the smaller number to the right Jason Cong

  49. IEEE Standard: four rounding modes: round to nearest even (default) round towards plus infinity round towards minus infinity round towards 0 round to nearest even: round digit < B/2 then truncate > B/2 then round up (add 1 to ULP: unit in last place) = B/2 then round to nearest even digit (LSB=1, add 1, otherwise, truncate => LSB is 0 after rounding) it can be shown that this strategy minimizes the mean error introduced by rounding Rounding Methods Jason Cong

  50. Denormalized (Subnormal) Numbers 2-bias denorm gap 1-bias -bias 2 2 0 2 Suppose B = 2, 3-bit mantissa The gap between 0 and the next representable number is much larger than the gaps between nearby representable numbers. IEEE standard uses denormalized numbers (exp. =0; significand <>0) to fill in the gap, making the distances between numbers near 0 more alike. 2-bias 1-bias -bias 2 2 0 2 p-1 bits of precision p bits of precision same spacing, half as many values! NOTE: PDP-11, VAX cannot represent subnormal numbers. These machines underflow to zero instead. Jason Cong

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