FPGA prototyping for fast and efficient verification of ASIC H.264 decoder

1. FPGA prototyping for fast and efficient verification of ASIC H.264 decoder -Basavaraj Mudigoudar Thesis defense for M.S. in EE, UTA, Apr 2006

4. Overview of H.264 Technology • Developed by JVT- Joint Video Team formed by VCEG of ITU-T and MPEG of ISO/IEC • ISO/IEC JTC1/SC29 14496-10 (MPEG-4 part 10) • Also ITU-T Recommendation H.264 / AVC • Uses advanced video coding algorithms • 3:1 coding efficiency over MPEG-2 • Supports small screens to Digital cinema

5. Overview of H.264 Salient features • Well defined profiles and levels • Hybrid block based compression • Intra prediction to reduce spatial correlation • Integer DCT to overcome round-off errors • Quantization to control bit rate • In-loop de-blocking to reduce coding artifacts • CABAC and CAVLC for efficient coding

6. Overview of H.264 Salient features (contd...) • Inter prediction to reduce temporal correlation • Variable block sizes from 16X16 up to 4X4 • Multiple reference frames for better compression • Up to ¼ pixel accuracy for motion vectors • Support for interlace and progressive • Uses PicAFF and MBAFF • Error resilience tools like ASO and FMO

7. Overview of H.264 Profiles and levels • Levels specify the upper limit on frame resolution, frame rate, bit rate, etc.

8. Overview of H.264 Encoding process

9. H.264 NALU IN Video out YUV4:2:0 Entropy Decoding Inverse Transform De-blocking Filter + Intra prediction Intra/Inter selection Inter prediction (motion compensation) Frame Buffer Overview of H.264 Decoding process

10. ASIC Implementation Need • Consumer electronics require video codec implementation to be • Low power • Low cost • Compact • Stand alone • Insufficient computing power in DSPs • ASIC is the logical choice

11. ASIC Implementation Guidelines • Compliance to the standard • Complete hardware implementation • Target or platform independent implementation • Common code base for ASIC and FPGA prototyping • New verification methodologies • Hardware level verification and prototyping

12. Design specification Design partitioning Coding of modules Functional verification Incorrect Results Correct System level integration Functional verification Incorrect Results Correct Design complete ASIC Implementation Design process

13. Input stream Memory Mgmt. Entropy decoding Inter prediction Ref. Picture Mgmt. Interconnect Inverse Transform Intra prediction Display Buf. Mgmt. De-blocking filter Output video ASIC Implementation ASIC modules of H.264 decoder core

14. ASIC Implementation Hardware description language • VHDL is a IEEE 1076 standard • It is a technology or vendor independent language • It is easily portable and reusable • Modular level design and system integration are easy • It is supported by both FPGA vendors and ASIC foundries for fabrication • Supported by EDA tools

15. Functional verification Verification is a process of checking whether the design meets the specifications for which it was designed Overview • 50-60 % of time and efforts of design teams • Adds to the NRE (Non-recurring Engineering) cost • time to market is important • Thorough functional verification is crucial • ASIC re-spins are unaffordable and time consuming

16. Simulation based verification Overview • DUT (Design Under Test) is simulated through simulation software • Test-benches are used to provide input test vectors • Results can be manually or automatically verified • Signal changes can be viewed in Waveform analyzer • Single platform system

17. Simulation based verification Advantages • Setup is simple, quick and easy • Highest level of controllability and observability • Complete feedback of the verification process • Direct interaction with minimum abstraction • Waveform analyzers can be used to observe changes in every signal or port during and after the verification process • No additional hardaware cost or porting efforts.

18. Simulation based verification SimVision, Waveform analyzer from Cadence Design systems

19. Simulation based verification Limitations • time consumed in simulating a digital design increases with the complexity of the design • Simulation takes an inordinately large amount of computing resources • memory requirements of simulation tool increase with the complexity of the design • Verification of Interfaces hard • Actual Hardware verification is not possible

20. Simulation based verification Simulation results NC-VHDL simulator from Cadence Design systems, on Pentium-4 3.0 GHz system with 1 GB DDR2 RAM

21. Emulation based verification Overview • Emulators use hardware accelerators • DUT is loaded into programmable emulator platform • Simulations are carried out in the emulator hardware • Test-benches are used to provide input test vectors • Signals to be monitored should be specified in advance • Results can be manually or automatically verified • Signal changes can be viewed in Waveform analyzers • Multiplatform system

22. Design specification Design partitioning VHDL Coding Emulation environment Design partitioning User inputs for signal monitoring Programming accelerator Monitor signals Incorrect Results Correct Design complete Emulation based verification Emulation process

23. Emulation based verification Advantages • Verification is 100 to 10000 times faster than simulation. • Emulation gives controllability and observability with certain level of abstraction • Partial to complete feedback from the verification process • Can simulate multi-million gate ASIC design. • Emulators are scalable and have various standard interfaces and built-in bus functional models (BFM)

24. Emulation based verification Limitations • Emulator platforms are expensive • They run at a speed up to 2 MHz which is still slow for some applications • Design complexity decides speed of operation and number of ports that can be observed • Time taken by compiler tools increase with complexity • Verification of Interfaces is hard • Actual Hardware level verification not possible

25. FPGA Field Programmable Gate Array Technology • Introduced in mid 1980s • Has programmable logic blocks and interconnects • Reconfigurable ASIC • Ideal for prototyping and system level testing • Verification of Interfaces can be performed • Actual Hardware level and in-system testing possible

26. FPGA How to decide on the device • Capacity of the FPGA • Speed of operation • Logic resources • Synthesis and implementation tools • IP cores and interface logic • Availability of Off the shelf boards

27. FPGA Device used and its features • Virtex4-LX100 from Xilinx Inc. • can operate at frequencies up to 500 MHz • Virtex-4LX100 has 100,000 logic cells • DSP specific blocks that are high performance versatile arithmetic units • 4,320 K bits of block RAM and high performance external memory interface • Optimized memory modules and DSP blocks

28. Prototyping board How to decide on the board • Interfaces present on the board • Reusability for other projects • Cost of the board • Learning time • Additional software and hardware requirements • Data transfer rate

29. Prototyping board Board used and its features • DN8000K10PCI board from The Dini Group • Hosts Virtex-4 LX and FX devices • 2 Slots of DDR2 memory addressable up to 4 GB • Serial port, PCI port and USB port • programmable clock generators • 200-pin expansion connectors • Digital Video Interface (DVI) daughter-card for display

30. Prototyping board

31. Prototyping based verification Overview • Proposed technique uses prototyping boards • DUT is synthesized for the FPGA on the board • Ports are pin locked with proper interfaces • Data tapping logic is introduced at memory controller • Data tapping is controlled externally on the fly • Test sequences are streamed to the board • Monitored data is trasfered to computer • Results can be manually or automatically verified

32. Prototyping based verification Advantages • Unmatched performance in speed of operation • Can work at real-time speeds or faster • Cost effective • Robust and exhaustive verification possible • Verification of interfaces is possible • Hardware level verification and testing possible • Saves lot of design time and NRE costs • Shortest time to market

33. Prototyping based verification Limitations • Reduced observability • Signals within the modules cannot be monitored • Technique can quickly identify the problem but does not give much insight to resolve the same • Recompilation time is generally higher • less useful in the initial stages of the design

34. Results Verification time (4CIF sequence)

35. Results Verification time (CIF sequence)

36. Results Verification time (QCIF sequence)

37. Design partitioning Design coding Module level verification System level verification (with simulation) Prototyping System level verification (with prototyping) System level verification (with Emulation) Results Design time line Simulation based verification Emulation based verification Prototyping based verification (proposed) 1 4 6 10 14 18 ASIC Design time (months)

38. Results Comparison chart

39. Demonstration

40. Conclusions • Proposed technique can save a lot on design time and project costs • Reduce time to market • Thorough and robust verification of ASIC is possible • Can perform hardware level verification • Requires tight coupling with simulation • Requires faster data exchange to monitor large data • Ideal for block based data processing designs

41. Future research • Automated techniques to capture and monitor data • Interface with simulation for an integrated environment • Fast data transfer techniques and interfaces • Techniques to verify data in the hardware

42. References [1] MPEG-4 : ISO/IEC JTC1/SC29 14496-10: Information technology - Coding of audio-visual objects - Part 10: Advanced Video Coding, ISO/IEC, 2005 [2] H.264: International Telecommunication Union, Recommendation ITU-T H.264: Advanced Video Coding for Generic Audiovisual Services, ITU-T, 2003 [3] Synplicity Inc., “ASIC Prototyping Using Off-the-Shelf FPGA Boards”, white paper, Jan 2006. http://www.techonline.com/pdf/pavillions/synplicity/synplicity_ prototyping.pdf [4] K. Kwon, A.Tamhankar and K.R.Rao, “Overview of MPEG-4 Part 10”. Journal of Visual Communication and Image Representation, Vol. 17, Issue 2, pp. 186-216, Apr 2006. [5] ITU-T website for H.264 standard, http://www.itu.int/rec/T-REC-H.264/en, Apr 2006. [6] G. Sullivan, P. Topiwala and A. Luthra, “The H.264/AVC advanced video coding standard: overview and introduction to the fidelity range extensions”. SPIE Conference on Applications of Digital Image Processing XXVII, vol. 5558, pp 53-57, 2004. [7] I. Amer, W. Badawy, and G. Jullien, “Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC)” IEEE workshop on signal processing systems, pp. 275-279, Oct 2004. [8] A. Puri, X. Chen and A. Luthra, “Video coding using the H.264/MPEG-4AVC compression standard”, Signal Processing: Image Communication, vol. 19, issue9, pp. 793-849, Oct 2004.

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44. References [18] W.I. Baker and A. Mahmood, “An analysis of parallel synchronous and conservative asynchronous logic simulation schemes”,Proceedings of sixth IEEE Symposium on Parallel and Distributed Processing, pp. 92 – 99, Oct 1994. [19] M.L. Bailey, “A time-based model for investigating parallel logic-level simulation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, issue 7, pp.  816 – 824, Jul 1992. [20] Cadence Design systems, website for information on NC-VHDL simulator, http://www.cadence.com/products/functional_ver/nc-vhdl/index.aspx, Apr 2006. [21] H. N. Nguyen and M. Thill, “Design verification based on hardware emulation”,Proceedings of Seventh IEEE International Workshop on Rapid System Prototyping, pp. 2 – 4, Jun 1996. [22] W.I. Baker and A. Mahmood, “An analysis of parallel synchronous and conservative asynchronous logic simulation schemes”,Proceedings of sixth IEEE Symposium on Parallel and Distributed Processing, pp. 92 – 99, Oct 1994. [23] M.L. Bailey, “A time-based model for investigating parallel logic-level simulation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, issue 7, pp.  816 – 824, Jul 1992. [24] Cadence Design systems, website for information on NC-VHDL simulator, http://www.cadence.com/products/functional_ver/nc-vhdl/index.aspx, Apr 2006.

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46. Thank you