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Subject of paper :

Subject of paper :. VHPI-compatible Simulation and Test Generation System. Dmitriy Speranskiy, Ivan Ukolov Russian State Open Technical University for Railway Transportation Saratov State University. Problem statement. Develop a software system performing the following functionality :

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Subject of paper :

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  1. Subject of paper: VHPI-compatible Simulation and Test Generation System Dmitriy Speranskiy, Ivan Ukolov Russian State Open Technical University for Railway Transportation Saratov State University East-West Design & Test Symposium 2009

  2. Problem statement Develop a software system performing the following functionality: • translation of the combinational and sequential circuits of the catalogs of ISCAS'85 and ISCAS'89 into VHDL-description with the single stuck-at faults support; • logic simulation of the fault-free digital circuits, as well as faulty circuits simulation by the given stimuli; • tests generation; • obtaining diagnostic information by the simulation results; • viewing waveforms; • extensible functional capabilities of the system. East-West Design & Test Symposium 2009

  3. Testbench A typical VHDL-testbench consists of three main components: • Stimulus Generator – drives the UUT with some input vectors; • Unit Under Test – represents the model undergoing verification; • Verifier – performs the UUT outputs checking, encountered errors reporting, model responses with the expected results comparison. East-West Design & Test Symposium 2009

  4. Simple testbench Stimulus Generator UUT Verifier Test Vector Response East-West Design & Test Symposium 2009

  5. Adaptive testbench Response Feedback Model State Stimulus Generator UUT Verifier Test Vector Response Expected Response East-West Design & Test Symposium 2009

  6. VHPI VHPIprovides the following functionality: • access to static VHDL design data; • access to dynamic VHDL objects; • simulation interaction; • simulation control; • foreign model instantiation and intercommunication mechanism. East-West Design & Test Symposium 2009

  7. System architecture Converter ISCAS’85, ISCAS’89 net list format (.isc, .ben, .bench, .flt) .vhd – VHDL source code .flist – fault set for VHDL-model VHDL Simulator Test Vectors ATPG(VHPI) UUT(VHDL) Clock Reset Simulation results, tests, diagnostic info, waveforms, etc. Response Feedback East-West Design & Test Symposium 2009

  8. Circuit translation INPUT(G0) INPUT(G1) INPUT(G2) INPUT(G3) OUTPUT(G17) G5 = DFF(G10) G6 = DFF(G11) G7 = DFF(G13) G14 = NOT(G0) G17 = NOT(G11) G8 = AND(G14, G6) G15 = OR(G12, G8) G16 = OR(G3, G8) G9 = NAND(G16, G15) G10 = NOR(G14, G11) G11 = NOR(G5, G9) G12 = NOR(G1, G7) G13 = NOR(G2, G12) library IEEE, base_elements; use IEEE.STD_LOGIC_1164.all; use base_elements.components.all; entity S27 is port( clk : in STD_LOGIC; reset : in STD_LOGIC; input : in STD_LOGIC_VECTOR(0 to 3); output : out STD_LOGIC_VECTOR(0 to 0)); end S27; architecture S27_arch of S27 is signal G7 : STD_LOGIC; … signal G10 : STD_LOGIC; begin … dff1: dff port map(clk, reset, G10, G5); … nand1: nand2 port map(reset, G16, G15, G9); end S27_arch; East-West Design & Test Symposium 2009

  9. Circuit translation G1 /0 G2 /0 G3 /0 G5 /0 G6 /1 G7 /0 G8 /0 /1 G9 /0 G10 /0 /1 G11 /0 /1 G12 /0 /1 G13 /0 /1 G14 /0 /1 G15 /1 G16 /1 G17 /0 /1 G8->G15 /0 G8->G16 /0 G11->G6 /0 /1 G11->G10 /0 G12->G13 /0 G12->G15 /0 G14->G8 /1 G14->G10 /0 G1 /0,G1,0 G2 /0,G2,0 G3 /0,G3,0 G5 /0,G5,0 G6 /1,G6,1 G7 /0,G7,0 G8 /0,G8,0 G8 /1,G8,1 G9 /0,G9,0 G11 /0,G11,0 G11 /1,G11,1 G15 /1,G15,1 G16 /1,G16,1 G17 /0,G17,0 G17 /1,G17,1 G8->G15 /0,or1:s2,0 G8->G16 /0,or2:s2,0 G11->G6 /0,dff2:s,0 G11->G6 /1,dff2:s,1 G11->G10 /0,nor1:s2,0 G12->G13 /0,nor4:s2,0 G12->G15 /0,or1:s1,0 G14->G8 /1,and1:s1,1 G14->G10 /0,nor1:s1,0 East-West Design & Test Symposium 2009

  10. VHPI-application: interface class SerialSimulator : public AbstractSerialAtpg { void initialization(int inputs, int outputs, int faults) {…} vector<string> generateInputVectors() {…} void onOutputVectors(intinstanceId, const vector<string> &outputs) {…} void onFinished() {…} void finalization() {…} } East-West Design & Test Symposium 2009

  11. VHPI-application: example vector<string> SerialSimulator::generateInputVectors() { return FileUtils::read(“input.txt”, inputs); } void SerialSimulator::onOutputVectors(int instanceId, const vector<string> &outputs) { FileUtils::write(“output.txt”, outputs); } void SerialSimulator::onFinished() { stop(); } East-West Design & Test Symposium 2009

  12. User interface East-West Design & Test Symposium 2009

  13. Results East-West Design & Test Symposium 2009

  14. Thank you for your attention East-West Design & Test Symposium 2009

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