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VLSI electronics for the read-out of radiation sensors Angelo Rivetti – INFN - Torino

VLSI electronics for the read-out of radiation sensors Angelo Rivetti – INFN - Torino. Topics. Introduction Architectures for read-out ASICs Why deep submicron CMOS? A detailed example: the ALICE SDD front-end. Why integrated ?.

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VLSI electronics for the read-out of radiation sensors Angelo Rivetti – INFN - Torino

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  1. VLSI electronics for the read-out of radiation sensors Angelo Rivetti – INFN - Torino Angelo Rivetti – INFN Sezione di Torino

  2. Topics • Introduction • Architectures for read-out ASICs • Why deep submicron CMOS? • A detailed example: the ALICE SDD front-end Angelo Rivetti – INFN Sezione di Torino

  3. Why integrated ? • Historically, dedicated integrated circuits came into play in nuclear electronics with the advent of silicon detectors. • Nowadays they are used to read-out most radiation detectors, including gas detectors • The possible use of APDs as an alternative to PMTs further increase the range of application of custom integrated I.Cs. • The use of I.Cs is motivated by the need of reading many channels minizing material and power consumption Angelo Rivetti – INFN Sezione di Torino

  4. The LHC scale The LHC detectors need an unprecedented number of electronics channels… Angelo Rivetti – INFN Sezione di Torino

  5. ALICE Silicon pixels: 0.2 m2, 9.3Mch Silicon drift: 1.3m2, 133kch Silicon strip: 4.9m2, 2.6Mch TPC: Volume 88m3, 1Mch … and many others… Angelo Rivetti – INFN Sezione di Torino

  6. ATLAS & CMS In term of number of channels, ALICE is dwarfed by ATLAS & CMS CMS 210m2 silicon microstrip sensors 9.6 Mch ATLAS 61m2 silicon microstrip sensors 6.3 Mch Angelo Rivetti – INFN Sezione di Torino

  7. A detector example You have to read-out something like this….(SDD of ALICE) Many independent channels have to be read Angelo Rivetti – INFN Sezione di Torino

  8. Basic design choices Selection of the architecture From system specs to System partitioning Technology choice Angelo Rivetti – INFN Sezione di Torino

  9. S&H Architecture selection (1) Analog read-out + • No info loss • Amplitude preserved • Easier to debug - • Big amount of data • Analog data handling • Very common for the read-out of silicon microstrip Angelo Rivetti – INFN Sezione di Torino

  10. Analog read-out example The APV chip for the CMS tracker 128 analog channels Preamp & analog pipeline Analog deconvolution processor CMOS 0.25mm technology 46.8 mm2 2mW/channel Reference: L.L Jones et al. The APV25 Deep Submicron ReadOut Chip http://lebwshop.home.cern.ch/lebwshop/LEB99_Book/Tracker/Jones.pdf Angelo Rivetti – INFN Sezione di Torino

  11. VTH Architecture selection (2) Binary read-out + • Simple • Fast • Minimum amount of data - • No information on amplitude • More difficult to debug • Standard for the read-out of pixel detectors • Common also for strip detectors Angelo Rivetti – INFN Sezione di Torino

  12. Binary read-out example The ABCD chip for the ATLAS microstrip 128 channels Preamp & discriminator Digital pipeline 46.8 mm2 2mW/ch BiCMOS 0.8mm rad-hard Reference: W. Dabrowski et al. Design an performance of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker IEEE TNS, vol. 47, no. 6, Dec. 2000 Angelo Rivetti – INFN Sezione di Torino

  13. ADC Architecture selection (3) Mixed-mode readout - • Large data volume • Mixed-mode IC more difficult to design + • No information loss • Robust • We will see more on this later… Angelo Rivetti – INFN Sezione di Torino

  14. Mixed-mode readoutexample The ALTRO chip for the ALICE TPC 16 ADC Embedded digital processing Digital tail cancellation CMOS 0.25mm technology 64 mm2 16mW/ch @ 10 MSPS Preamp on a separate IC Reference: R. Esteve Bosch, L. Musa, et. al The ALTRO chip: A 16 Channel A-D converter and digital processor for Gas Detectors IEEE NSS – MIC, Norfolk, Nov. 2002. Angelo Rivetti – INFN Sezione di Torino

  15. vnoise2Ct2K2(n) ENC2 = inoise2K1(n)ts+ ts Why deep-submicron CMOS ? CMOS already popular in the design of front-end Bipolar traditionally better at short shaping time, due to the base current shot noise Angelo Rivetti – INFN Sezione di Torino

  16. Process trends in CMOS technologies Angelo Rivetti – INFN Sezione di Torino

  17. Interconnection example Angelo Rivetti – INFN Sezione di Torino

  18. Digital vs analog • The scaling of CMOS technologies is driven by the need of improving the perfomance of digital ICs • The need of analog design not taken too much into account • Analog features come usually later • Digital circuits improve with scaling, but what about analog ones? Angelo Rivetti – INFN Sezione di Torino

  19. W mn COX 2 IDS gm = L Analog properties and process scaling: (1) tOX scales, k=mCox =meOX/tOX scales => for the same W /L and the same current gm improves k for different technologies (NMOS devices) This is for strong inversion… Angelo Rivetti – INFN Sezione di Torino

  20. Analog properties and process scaling: (2) • k=mCox scales => for the same W and L: • W.I.-S.I. boundary moves towards higher currents: Ilim=2nk(W/L)UT2 gm/IDS max in W.I. Angelo Rivetti – INFN Sezione di Torino

  21. K a S  2 V C WLf ox Analog properties and process scaling (3) • tox scales => Cox and k=mCox increase. For the same W and L: • matching improves: • flicker noise is reduced: • transconductance increases: Angelo Rivetti – INFN Sezione di Torino

  22. gds gds Vdd=5V Vdd=1.6V 0 0 Vdd-VTn VTp Vdd Vdd-VTn Vdd VTp Problem: SC circuits operation (1) ck Vin ck_b Angelo Rivetti – INFN Sezione di Torino

  23. ck Vin CL ck_b Problem: SC circuits operation (2) W/L=200/0.36 CL=20pF fin=2.5MHz Angelo Rivetti – INFN Sezione di Torino

  24. Problem: substrate noise digital analog P- P+ Angelo Rivetti – INFN Sezione di Torino

  25. Analog properties and process scaling: (3) • tox scales => Vdd must be scaled as well • Minimum power consumption for class A analog circuits: DV is the fraction of the power supply not used for signal swing Angelo Rivetti – INFN Sezione di Torino

  26. Analog properties : summary • Transistor properties improve, but signal swing is reduced • => is there an optimum? • Optimal power/performance trade-off may occur with 0.35 - 0.25 mm! • (A. J. Annema, IEEE Trans. On Cicuits and Systems, II vol 46, No. 6, June 1999). • In 0.25 mm CMOS (2.5V) conventional architectures still work! Angelo Rivetti – INFN Sezione di Torino

  27. SiO2 gate n+ n+ P- Effect of radiation on MOS (1) • The sensitive part is the oxide • A ionizing particle creates electron- hole pairs • In the oxide, the mobility of holes is much smaller than the one of electrons (7-12 orders of magnitude) • Three main effects arise: • => threshold shift of the main device • => threshold shift of parasitic devices • => interface state generation Angelo Rivetti – INFN Sezione di Torino

  28. Effect of radiation on MOS (2) Angelo Rivetti – INFN Sezione di Torino

  29. Vdd Vss polisilicon ++++++++++ source n+ nwell Effect of radiation on MOS (3) Inter-device leakage via thick oxide Angelo Rivetti – INFN Sezione di Torino

  30. G D S D S G Rad-tol design approach • Thin oxide + enclosed layout & guardring (ELT) = radiation tolerance • Deep submicron CMOS is a good choice for rad-tol IC for HEP • Single Event Effect may worsen, but... • Extesively studied by the CERN RD49 collaboration Angelo Rivetti – INFN Sezione di Torino

  31. Silicon Drift Detector (SDD) • Drift of charged particles in silicon • 2-dimension measurement • 20mm resolution • dE/dx measurement with analog read-out • “few” read-out channel • drift speed 5mm/ns • but…v=mE, m T-2.4! Angelo Rivetti – INFN Sezione di Torino

  32. ..... Angelo Rivetti – INFN Sezione di Torino

  33. SDD system specifications • Total number of channels: 130000 • Input charge 500e- to 250000e- • Input signal: Gaussian (amplitude 10nA - 1.6mA; s 10ns – 30ns) • Shaping time: 40ns • Sampling frequency: 40 MS/s • Bits/sample: 10 • Noise < 500 e- rms (250e- rms) • Power/channel < 5mW • Front-end board: 8 x 2 cm2 • System dead time: < 1ms • Reduce material as much as possible Angelo Rivetti – INFN Sezione di Torino

  34. System partitioning (1) • On the front-end board space for 8 VLSI chips • Optimize the system for minimum output connections • Preamplifier • Sampling: 1 FADC/channel: impractical for power and space • First level analog buffer (SCA) + slower ADC • Commercial slower ADC: impractical for space • Commercial slower ADC: analog data handling • No analog processing, ADC on the front-end chip • Front-end integration: 64 channel/chip as a compromise between space and yield (8 FE chips per detector) Angelo Rivetti – INFN Sezione di Torino

  35. System partitioning (2) • Output lines @ 40MHz clock: two 10bit busses/chip • 16 busses per detector: 160 lines ( too many!) • Solution: local digital buffering (2nd chip) • 10bit to 8 bit reduction on the digital buffer • Two 8 bit busses per detector (=less material) • Only one 8 bit bus per front-end with acceptable dead time • 8 chips on the FE board, 16 chips per detector Angelo Rivetti – INFN Sezione di Torino

  36. A look at the system... Angelo Rivetti – INFN Sezione di Torino

  37. Analog memory Preamp SAR ADC ... and at the chip Angelo Rivetti – INFN Sezione di Torino

  38. Preamplifier specs • Input capacitance capacitance: 1 - 3 pF • Input signal 1 to 8 mips • Peaking time < 50 ns (separation of close tracks) • Noise < 500 e- r.m.s • Power consumption < 2mW/ch Angelo Rivetti – INFN Sezione di Torino

  39. PA In SH Out BH Vref Preamplifier block diagram (1) Angelo Rivetti – INFN Sezione di Torino

  40. Vfeed Rz Rf Cf Cz PA In SH Out If BH Vref Preamplifier block diagram (2) Angelo Rivetti – INFN Sezione di Torino

  41. VB VB VBC VBC Vcas In Core amplifier schematic Angelo Rivetti – INFN Sezione di Torino

  42. VB VB VB VB Vref Out In_sh VB VB Baseline holder schematic Angelo Rivetti – INFN Sezione di Torino

  43. Vin Vout Cload VB Buffer schematic Angelo Rivetti – INFN Sezione di Torino

  44. SH Shaper time constant tuning Out Angelo Rivetti – INFN Sezione di Torino

  45. Response to 1 mip DV = 164 mV Tp = 32 ns (s) Angelo Rivetti – INFN Sezione di Torino

  46. Vfeed Rz Rf Cf Cz PA In If Layout example Angelo Rivetti – INFN Sezione di Torino

  47. Memory Channel Schematic Digital Control Logic G. Anelli et al. IEEE TNS, vol48 (3), pp. 435 – 439) June 2001 IN SW_W SW_R SW_F OUT + Vref_w Vref_r Angelo Rivetti – INFN Sezione di Torino

  48. V V GND GND n+ n+ n+ n+ p+ p+ Which Capacitors for Storage? (1) PMOS Transistor without S and D Accumulation Region NMOS Transistor Inversion Region n well p substrate p substrate Angelo Rivetti – INFN Sezione di Torino

  49. Which Capacitors for Storage? (2) Angelo Rivetti – INFN Sezione di Torino

  50. Design of a compact CMOS ADC • Conventional SAR based successive approximation scheme • Good trade-off between speed, area and power • Clock speed: 20 MHz • Single rail operation Angelo Rivetti – INFN Sezione di Torino

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