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SCHEDULING AND TIMING ANALYSIS OF HW/SW ON-CHIP COMMUNICATION IN MP SOC DESIGN

SCHEDULING AND TIMING ANALYSIS OF HW/SW ON-CHIP COMMUNICATION IN MP SOC DESIGN. Contents. Introduction Motivation Communication Scheduling and HW/SW Timing Analysis Experimental Results Conclusion. Introduction. On-chip Communication Architecture in MP SoC design

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SCHEDULING AND TIMING ANALYSIS OF HW/SW ON-CHIP COMMUNICATION IN MP SOC DESIGN

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  1. SCHEDULING AND TIMING ANALYSIS OF HW/SW ON-CHIP COMMUNICATION INMP SOC DESIGN

  2. Contents • Introduction • Motivation • Communication Scheduling and HW/SW Timing Analysis • Experimental Results • Conclusion

  3. Introduction • On-chip Communication Architecture in MP SoC design • On-chip Communication Design • Design of HW/SW Communication Architecture • Mapping and scheduling of on-chip communication • Contribution of this work is the consideration of both of • Dynamic behavior of SW communication architecture • Physical communication buffer sharing

  4. Preliminaries • Mapping/Allocation • Communication Scheduling

  5. Motivation

  6. Extended Task Graph (ETG)

  7. Communication Delay Model • Communication Delay • Communication Delay of SW Communication Architecture • Communication Delay of HW Communication Interface • Communication Delay of On-chip Communication Network

  8. Communication Scheduling and Timing Analysis • ILP for Scheduling Communication Nodes and Tasks of ETG • Data dependency constraints • Resource contention constraints – Processor and on-chip communication network

  9. ILP for Binary variable – Physical communication buffer contention constraints

  10. Heuristic Algorithm • List scheduling LIST (G(V,E),a) { I=1; Repeat { For each resource type k=1,2,…., nres { Determine candidate tasks Determine unfinished tasks Select nodes, such that Schedule the tasks at time by setting } } until ( is scheduled); Return (t); }

  11. Experiments

  12. Experimental Results • Execution delay of tasks in the H.263 system • Delay of software communication architecture • Software communication architecture delay measured by ISS.

  13. Execution Time of H.263 encoder

  14. Execution Time of JPEG and IS-95 example

  15. Conclusion • On-chip Communication Design • Design of HW/SW Communication Architecture • Mapping and scheduling of on-chip communication • Communication Scheduling and Timing Analysis • ILP Formulation • Heuristic • Consideration of • Dynamic behavior of SW communication architecture • Physical communication buffer sharing • Future Work • To extend the approach to thecomplicated On-Chip Network • To design On-Chip Communication Scheduler

  16. Thank you ^^

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