CS/COE0447 Computer Organization & Assembly Language

1. CS/COE0447Computer Organization & Assembly Language LECTURE NOTE Chapter 5

2. A Simple MIPS • Memory reference instructions • lw (load word) and sw (store word) • Arithmetic-logical instructions • add, sub, and, or, and slt • Control-transfer instructions • beq (branch if equal) • j (unconditional jump)

3. Implementation Overview • Send program counter (PC) to code memory and fetch an instruction • Read one or two registers • Depending on the instruction type, we need to do different actions with the values read from the register file • Instructions of a same type (e.g., memory) perform similar work

4. An Abstract Implementation • Combinational logic • ALU, adder • Sequential logic • Register file, instruction memory, data memory

5. Instruction Analysis • lw (load word) • Fetch instruction • Read a base register • Sign-extend the immediate offset • Add two values to get address • Access data memory with the address • Store the memory data to the destination register

6. Instruction Analysis, cont’d • add • Fetch instruction • Read two source registers • Add two values • Store the result to the destination register

7. Instruction Analysis, cont’d • j • Fetch instruction • Take the 26-bit immediate field • Shift left by 2 (to make 28-bit immediate) • Get 4 bits from the current PC and attach to the left of the immediate • Assign the value to PC • What about other instructions?

8. Components • ALU • We’ve already built this! • Memory • Instruction memory to supply instructions • Data memory to supply data • Data memory allows writing to it (store) • PC • Essentially a register • Update logic (increment/jump address)

9. Components, cont’d • Register file • 32 32-bit registers • 2 read ports, one write port • Immediate • Sometimes instruction contains immediate • We may sign-extend it • Support for branch and jump

10. Building Blocks

11. Instruction width is 4 bytes! Instruction memory here is read-only! PC keeps the current memory address from which instruction is fetched Instruction Fetch

12. For branches! Two reads at a time! Operand Fetch

13. Data to store! Imm. offset for address Load data from memory To be in a register! Handling Memory Instructions

14. Datapath so far j instruction not considered so far!

15. Instruction Format

16. Write register # selection ALU control bits from I[5:0] More Elaborated Design

17. A First Look at Control

18. Control Signals Overview • RegDst: which instr. field to use for dst. register specifier? • instruction[20:16] vs. instruction[15:11] • ALUSrc: which one to use for ALU src 2? • immediate vs. register read port 2 • MemtoReg: is it memory load? • RegWrite: update register? • MemRead: read memory? • MemWrite: write to memory? • Branch: is it a branch? • ALUop: what type of ALU operation?

19. Generic Control Sequence • For each fetched instruction • (decoding) • Select two registers to read from register file • Select the 2nd register input • Select ALU operation • Select if data memory is to be accessed • Select if register file is updated • Select what to assign to PC

20. Example: lw r8, 32(r18) • Let’s assume r18 has 1,000 • Let’s assume M[1032] has 0x11223344 I-Format

21. Example: lw r8, 32(r18) (PC+4) (PC+4) Branch=0 35 RegWrite (PC+4) 18 1000 8 0x11223344 RegDest=0 ALUSrc=1 8 1032 0 MemtoReg=1 32 0x11223344 32 32 MemRead 0x11223344

22. Control Sequence for lw • OPcode = 35 • RegDst = 0 • ALUSrc = 1 • MemtoReg = 1 • RegWrite = 1 • MemRead = 1 • MemWrite = 0 • Branch = 0 • ALUop = 0

23. Control Signal Table

24. ALU Control • Depending on instruction, we perform different ALU operation • Example • lw or sw: ADD • and: AND • beq: SUB • ALU control input (3 bits) • 000: AND • 001: OR • 010: ADD • 110: SUB • 111: SET-IF-LESS-THAN (similar to SUB)

25. ALU Control, cont’d • ALUop • 00: lw/sw, 01: beq, 10: arithmetic, 11: jump

26. ALU Control Truth Table

27. ALU Control Logic Design

28. Datapath w/ Jump

29. Functional Unit Used

30. Register File Implementation

31. Reg. File Impl., cont’d 0 1 1 0x11223344 0 0 0x11223344

32. What We Have Now

33. Resource Usage

34. Single-Cycle Execution Timing (in pico-seconds)

35. Single-Cycle Exe. Problem • The cycle time depends on the most time-consuming instruction • What happens if we implement a more complex instruction, e.g., a floating-point mult. • All resources are simultaneously active – there is no sharing of resources • We’ll adopt a multi-cycle solution • Use a faster clock • Allow different number of clock cycles per instruction

36. A Multi-cycle Datapath • A single memory unit for both instructions and data • Single ALU rather than ALU & two adders • Registers added after every major functional unit to hold the output until it is used in a subsequent clock cycle

37. Multi-cycle Approach • Reusing functional units • Break up instruction execution into smaller steps • Each functional unit is used for a specific purpose in any cycle • ALU is used for additional functions: calculation and PC increment • Memory used for instructions and data • At the end of a cycle, keep results in registers • Additional registers • Now, control signals are NOT solely determined by the instruction bits • Controls will be generated by a FSM!

38. Finite State Machine (FSM) • FSM • Memory element to keep current state • Next state function • Output function

39. Operations

40. Five Execution Steps • Instruction fetch • Instruction decode and register read • Execution, memory address calculation, or branch completion • Memory access or R-type instruction completion • Write-back • Instruction execution takes 3~5 cycles!

41. Step 1: Instruction Fetch • Access memory w/ PC to fetch instruction and store it in Instruction Register (IR) • Increment PC by 4 and put the result back in the PC • We can do this because ALU is not busy and we can use it • Actual PC Update is done at the next clock rising edge

42. Step 2: Decode and Reg. Read • Read registers rs and rt • We read both of them regardless of necessity • Compute the branch address in case the instruction is a branch • We can do this as ALU is not busy • ALUOut will keep the target address • We still don’t set any control signals based on the instruction type • Instruction is being decoded now in the control logic!

43. Step 3: Various Actions • ALU performs one of three functions based on instruction type • Memory reference • ALUOut <= A + sign-extend(IR[15:0]); • R-type • ALUOut <= A op B; • Branch: • if (A==B) PC <= ALUOut; • Jump: • PC <= {PC[31:28],IR[25:0],2’b00}; // verilog notation

44. Step 4: Memory Access… • If the instruction is memory reference • MDR <= Memory[ALUOut]; // if it is a load • Memory[ALUOut] <= B; // if it is a store • Store is complete! • If the instruction is R-type • Reg[IR[15:11]] <= ALUOut; • Now the instruction is complete!

45. Step 5: Register Write Back • Only memory load instruction reaches this step • Reg[IR[20:16]] <= MDR;

46. A (Refined) Datapath

47. Datapath w/ Control Signals

48. Final Version w/ Control

49. State Diagram, Big Picture

50. Handling Memory Instructions