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Analog VLSI Design. Nguyen Cao Qui. Introduction to the course. Name: “ Analog VLSI Design †Instructor: Nguyen Cao Qui email: ncqui@ctu.edu.vn Goals:
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Analog VLSI Design Nguyen Cao Qui
Introduction to the course • Name: “ Analog VLSI Design ” • Instructor: Nguyen Cao Qui email: ncqui@ctu.edu.vn • Goals: The goal of this course is to introduce the principles of operation, design and technology of Analog Integrated Circuits to Electrical Engineering students at Senior level. VLSI technology and analog integrated circuit design is covered with an emphasis on CMOS Technology. CMOS layout design and analog simulation tools (Cadence) are demonstrated and used. Students will do a design project and final exam at the end.
Introduction to the course • Number of credits : 3 (1: theory ; 2: homework + project +Seminar) • Textbooks: “CMOS: Circuit Design, Layout, and Simulation” R. Jacob Baker • Other Books: "CMOS Analog Circuit Design" Phillip E. Allen and Douglas R. Holdberg
Introduction to the course • Course Policies: * Homework + Project : 40% * Final Test :60%
CONTENTS • Chapter 1: Introduction to CMOS Design • Chapter 2: The Well • Chapter 3: The Metal Layers • Chapter 4: The Active and Poly Layers • Chapter 5: CAD Tools (Cadence) • Chapter 6: Resistors, Capacitors, MOSFETs • Chapter 7: Models for Analog Design • Chapter 8: The Inverter • Chapter 9: VLSI Layout Examples • Chapter 10: Current Mirrors • Chapter 11: Amplifiers • Chapter 12: Differential Amplifiers • Chapter 13: Operational Amplifiers I • Chapter 14: Voltage References • Chapter 15: Data Converter Fundamentals (ADC) • Chapter 16: Data Converter Fundamentals (DAC)
Chapter 1Introduction to CMOS Design • CMOS (complementary metal oxide semiconductor) • CMOS is used in most very large scale integrated (VLSI) or ultra-large scale integrated (ULSI) • "VLSI" : chips containing thousands or millions of MOSFETs. • "ULSI" : containing billions, or more, MOSFETs. • We focus simply on analog CMOS circuit design
Introduction to CMOS Design 1. The CMOS IC Design Process
The CMOS IC Design Process 1.1 Fabrication • CMOS integrated circuits are fabricated silicon wafers. • Each wafer contains chipsor "die" • The most common wafer size is 300 mm
2. CMOS Background • CMOS circuit design was invented in 1963 by Frank Wanlass • Circuit could be made with discrete complementary MOS devices, an NMOS and a PMOS NMOS PMOS
2. CMOS Background * Ex: CMOS Inverter
2. CMOS Background • Advantages of CMOS: • Low power • Layout on small area • Can be fabricated with few defects and low cost. 95% of ICs are fabricated in CMOS
3. Technology Scale Down * The Moore’s Law : Doubling every 18 months
Chapter 2: The Well * Studying the well to: • Understanding CMOS integrated circuit layout and design. • Understanding the performance limitations and parasitics. • Understanding the details of each fabrication (layout) layer.
Chapter 2: The Well * The Substrate (The Unprocessed Wafer) • CMOS circuits are fabricated on and in a silicon wafer • N-type wafer: doping with donor atoms, exp: phosphorus • P-type wafer: doping with acceptor atoms, exp: boron • P-type wafer: the most common substrate used • NMOS are fabricated directly in the p-type wafer • PMOS are fabricated in an "n-well."
Chapter 2: The Well * A Parasitic Diode
Chapter 2: The Well * Using the N-well as a Resistor
2.1 Patterning CMOS integrated circuits are formed by patterning different layers on and in the silicon wafer.
2.3 Resistance Calculation * Layout of Corners
Chapter 3: The Metal Layers • The metal layers: connect circuit elements (MOSFETs, capacitors, and resistors). • There are several metal layers when layout • These levels of metal are named metal1 (M1), metal2 (M2)…
3.1 The Bonding Pad • The interface between the die and the package
3.2 Design and Layout Using the Metal Layers 3.2.1 Metal1 and Via1
Intrinsic Propagation Delay The velocity The delay of the metal line Where
