MICROCONTROLERE

1. - Calculator pe un cip deoarece el conţine pe lângă CPU şi memorie şi interfeţe de intrare ieşire - Cele mai populare microcontrolere sunt 8051 produs prima data de firma Intel şi 68HC11 a firmei Motorola. MICROCONTROLERE

2. An 8-bit Microcontroller optimized for control applications. A Microcontroller derivative family based on the 8051 core. A Microcontroller because you can make a one-chip system with the one chip containing: Program & Data Memory I/O Ports Serial Communication Counters/Timers Interrupt Control logic A-to-D and D-to-A convertors & so on ... The 8051

3. - 8 Bit data path and ALU. - Easy interfacing. - 12 to 30 MHz versions available. ( 1 µsec to 400 ns for single cycle instructions). - Full instruction set including: Multiply and Divide. Bit set, reset, and test (Boolean instructions). - Variety of addressing modes. Features of the 8051

4. - 4K X 8 ROM - Program memory. - 128 x 8 RAM - Data memory. - Special function registers. - Serial I/O port. - 32 I/O lines. - Two 16-bit counter/timers. Features of the 8051 (cont'd)

5. 8051 Logic Symbol

6. 80C51 Block Diagram External Interrupts Timer 1 4k byte ROM 128 byte RAM Counter Inputs Interrupt Control Timer 0 CPU Bus Control Serial Port I/O Ports OSC TXD RXD P0 P2 P1 P3 (Address/Data)

7. - 64K X 8 ROM - Program memory. - 64K x 8 RAM - External data memory. - 256 x 8 RAM - Internal data memory. - 128 x 8 Special function registers (SFRs). - Bit addressing of 16 RAM locations and 16 SFRs. Addressing Space

8. Microcontrolerul 8051 are următoarele tipuri de memorie: memoria internă (On-Chip Memory) memoria externă de program (External Code Memory) memoria externă de date (External RAM) Memoria

9. Memoria 8051

10. Program Memory - 64K byte address space each for Program & Data. - EA pin disables internal ROM and activates external program memory and addressing.

11. Memoria de date • 128 bytes RAM intern • 64 Kbytes adresabil extern FFFFH Externă Internă FFH 00

12. - 128 bytes of RAM. - Directly addressable range: 00 to 7F hexadecimal. - Indirectly addressable range: 00 to FF hexadecimal. - Bit addressable space: 20 to 2F hexadecimal . - Four register banks: 00 to 1F hexadecimal. Internal Data Memory

13. Internal Data Memory END 8051 RAM 7F 30 FF . . . . . . . . . F8 2F BIT ADDRESSABLE 07 . . . . . . . . . 00 20 1F REGISTER BANK 3 20 17 REGISTER BANK 2 18 0F REGISTER BANK 1 08 R7 07 R6 R5 R4 REGISTER BANK 0 R3 R2 R1 00 R0

14. - 64K byte address space. - Indirectly addressable via R0 and R1 in 256 byte segments. - Entire space is indirectly addressable via the data pointer DPTR. External Data Memory

15. PORT 2 PORT 0 ALE P3.7 P3.6 PSEN External Bus Expansion 8051 A15 - A8: High byte of address AD7 - AD0: Data and low byte address ALE: Address latch enable RD: Read strobe WR: Write strobe PSEN: Program store enable

16. 8051 Timing State 1 State 2 State 3 State 4 State 5 State 6 State 1 State 2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 XTAL2 ALE _____ PSEN P0 PCL out PCL out PCL out Data sampled Data sampled Data sampled PCH out PCH out P2

17. External Program Memory 8051 A15 - A8 PORT2 ROM(S) ALE ADDRESS LATCH ADDRESS INPUTS AD7 - AD0 PORT0 A7 - A0 DATA OUTPUTS D7 - D0 PSEN OE

18. · 64K byte adress space. · Indirectly addressable via R0 and R1 in 256 byte segments. · Entire space in indirectly addressable via the data pointer DPTR. External Data Memory RAM(S) or I/O 8051 DECODE CE PORT 2 ALE ADDRESS INPUTS ADDRESS LATCH PORT 0 DATA OUTPUTS R/W WR OE RD

19. · RST pin is Schmitt trigger input. · External reset is asychronous to the internal clock. · RST pin must be high for at least two machine cycles while the oscillator is running. · Internal RAM not affected by reset, but indeterminate on power up. · Port pins in random state until oscillator starts and algorithm write 1's to them. · Reset sets PC to 0000. · Typical circuits: Reset +5V +5V 8051 80C51 10uF 2.2uF RST RST 8.2K

20. - 128 byte address space, directly addressable as 80 to FF hex. - 16 addresses are bit addressable: Set, Clear, AND, OR, MOV (those ending in 0 or 8). - This space contains: Special purpose CPU registers. I/O control registers. I/O ports. Special Function Register Space

21. Special Function Register Map Bit Addressable

22. CPU registers: - ACC : Accumulator. - B : B register. - PSW : Program Status Word. - SP : Stack Pointer. - DPTR : Data Pointer (DPH, DPL). Interrupt control: -IE : Interrupt Enable. -IP : Interrupt Priority. I/O Ports: - P0 : Port 0. - P1 : Port 1. - P2 : Port 2. - P3 : Port 3. Special Function Registers

23. TImers: - TMOD : Timer mode. - TCON : Timer control. - TH0 : Timer 0 high byte. - TL0 : Timer 0 low byte. - TH1 : Timer 1 high byte. - TL1 : Timer 1 low byte. Serial I/O: - SCON : Serial port control. - SBUF : Serial data registers. Other: - PCON : Power control & misc. Special Function Registers (cont'd)

24. CY AC F0 RS1 RS0 OV ---- P - CY : Carry Flag. - AC : Auxiliary Carry Flag. - F0 : Flag 0 (available for user). - RS1 : Register Select 1. - RS0 : Register Select 0. - OV : Arithmetic Overflow Flag. - P : Accumulator Parity Flag. PSW : Program Status Word RS1 RSO Register Bank Address 0 0 0 00h - 07h 0 1 1 08h - 0Fh 1 0 2 10h - 17h 1 1 3 18h - 1Fh

25. - Four 8-bit I/O ports. - Most have alternate functions. - Quasi-bidirectional: Soft pull-up when port latch contains a 1. Can be used as inputs (30Kohm average pullup). Strong pull-up for 2 CPU cycles during 0 to 1 transitions. I/O Ports

26. Port Configuration

27. - As an I/O port: No strong pull-up, outputs act as open drain. - As a multiplexed data bus: Tristate bus with strong pull-ups. 8-bit instruction bus, strobed by PSEN. Low byte of address bus, strobed by ALE. 8-bit data bus, strobed by WR and RD. - 3.2 mA outputs (about 8 LSTTL loads). Port 0

28. As an I/O port: Standard quasi-bidirectional. - Alternate functions: Only on some derivatives. - 1.6 mA outputs (about 4 LSTTL loads). Port 1

29. - As an I/O port: Standard quasi-bidirectional. - Alternate functions: High byte of address bus for external program and data memory accesses. - 1.6 mA outputs (about 4 LSTTL loads). Port 2

30. - As an I/O port: Standard quasi-bidirectional. - Alternate functions: Serial I/O - TXD, RXD Timer clocks - T0, T1 Interrupts - INT0, INT1 Data memory - RD, WR - 1.6 mA outputs (about 4 LSTTL loads). Port 3

31. - Two 16-bit Counter/Timers: Up counters, can interrupt on overflow. - Counts: CPU cycles (crystal/12). External input (max. half CPU rate). - Four Operation Modes. Counter / Timers

32. - Timer Mode 0 : Emulates 8048 counter/timer (13-bits). 8-bit counter (TL0 or TL1). 5-bit prescaler (TH0 or TH1). - Timer Mode 1 : Simple 16-bit counter. - Timer Mode 2 : 8-bit auto-reload. Counter in TL0 or TL1. Reload value in TH0 or TH1. Provides a periodic flag or interrupt. Timer Modes

33. - Timer Mode 3 : Splits timer 0 into two 8-bit counter/timers. First counter (TLO) acts like mode 0, without prescaler. Second counter (TH0): Counts CPU cycles. Uses TR1 (timer 1 run bit) as enable. Uses TF1 (timer 1 overflow bit) as flag. Uses Timer 1 interrupt. Timer 1 (when timer 0 is in mode 3 ): Counter stopped if in mode 3. Running in mode 0, 1, or 2. Has gate (INT1) and external input (T1), but no flag or interrupt. May be used as a baud rate generator. Timer Modes (cont'd)

34. Counter/Timer in 16-bit (Mode 1) The Gate input controls whether the Counter runs while gated by the interrupt signal or not.

35. - GATE : Permits INTx pin to enable/disable counter. - C/T : Set for counter operation, reset for timer operation. - M1, M0 : 00 : Emulate 8048 counter/timer (13-bits). 01 :16-bit counter/timer. 10 : 8-bit auto-reload mode 11 :Timer 0 = two 8-bit timers. Timer 1 Counting disabled. Timing function allowed. Can be used as Baud Rate generator. TMOD : Counter/Timer Mode Register GATE C/T M1 M0 GATE C/T M1 M0 Timer 1 Timer 0

36. - TF1, TF0 : Overflow flags for Timer 1 and Timer 0. - TR1, TR0 : Run control bits for Timer 1 and Timer 0. Set to run, reset to hold. - IE1, IE0 : Edge flag for external interrupts 1 and 0. * Set by interrupt edge, cleared when interrupt is processed. - IT1, IT0 : Type bit for external interrupts. * Set for falling edge interrupts, reset for 0 level interrupts. * = not related to counter/timer operation. TCON : Counter/Timer Control Register TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

37. - Full duplex UART. - Four modes of operation: Synchronous serial I/O expansion. Asynchronous serial I/O with variable baud rate. Nine bit mode with variable baud rate. Nine bit mode with fixed baud rate. - 10 or 11 bit frames. - Interrupt driven or polled operation. - Registers: SCON - Serial port control register. SBUF - Read received data. - Write data to be transmitted. PCON - SMOD bit. Serial Interface

38. TXD and RXD are the serial output and input pins (Port 3, bits 1 and 0). Mode 0: Shift Register Mode. Serial data is transmitted/received on RXD. TXD outputs shift clock. Baud Rate is 1/12 of clock frequency. Mode 1: 10-bits transmitted or received. Start (0), 8 data bits (LSB first), and a stop bit (1). Baud Rate Clock is variable using Timer 1 overflow or external count input. Can go up to 104.2KHz (20MHz osc.). Mode 2: 11-bits transmitted or received. Start (0), 8 data bits (LSB first), programmable 9th bit, and stop bit (1). Baud Rate programmable to either 1/32 or 1/64 oscillator frequency (625KHz for 20MHz osc.). Mode 3: 11-bit mode. Baud Rate variable using Timer 1 overflow or external input. 104.2 KHz max. (20 MHz osc.). Serial Interface Modes of Operation

39. Serial Communication Modes 2 and 3 allow one "Master" 8051 to control several "Slaves": The serial port can be programmed to generate an interrupt if the 9th data bit = 1. The TXD outputs of the slaves are tied together and to the RXD input of the master. The RXD inputs of the slaves are tied together and to the TXD ouput of the master. Each slave is assigned an address. Address bytes transmitted by the master have the 9th bit = 1. When the master transmits an address byte, all the slaves are interrupted. The slaves then check to see if they are being addressed or not. The Addressed slave can then carry out the master's commands. Multi-Drop Communication

40. - SM0, SM1 = Serial Mode: 00 = Mode 0 : Shift register I/O expansion. 01 = Mode 1 : 8-bit UART with variable baud rate. 10 = Mode 2 : 9-bit UART with fixed baud rate. 11 = Mode 3 : 9-bit UART with variable baud rate. - SM2 : Mode 0 : Not used. Mode 1 : 1 = Ignore bytes with no stop bit. Mode 2,3 : 0 = Set receive interrupt (RI) on all bytes. : 1 = Set RI on bytes where bit 9 = 1. - REN = Enables receiver. - TB8 = Ninth bit transmitted (in modes 2 and 3). - RB8 = Ninth bit received: Mode 0 : Not used. Mode 1 : Stop bit. Mode 2,3 : Ninth data bit. - TI = Transmit interrupt flag. - RI = Receive interrupt flag. SCON : Serial Control Register SMO SM1 SM2 REN TB8 RB8 TI RI

41. - 5 Interrupt Sources (in order of priority): External Interrupt 0. Timer 0. External Interrupt 1. Timer 1. Serial Port. - Each interrupt type has a separate vector address. - Each interrupt type can be programmed to one of two priority levels. - External interrupts can be programmed for edge or level sensitivity. Interrupt System

42. - EA : Global interrupt enable. - ES : Serial interface. - ET1 : Timer 1. - EX1 : External interrupt 1. - ET0 : Timer 0. - EX0 : External interrupt 0. - 0 = Disabled. - 1 = Enabled. IE : Interrupt Enable Register EA ---- ---- ES ET1 EX1 ET0 EX0

43. Source Address IE0 03H TF0 0BH IE1 13H TF1 1BH RI&TI 23H Interrupt Vector Addresses The 8051 starts execution at 0000H after Reset.

44. - PS : Serial interface. - PT1 : Timer 1. - PX1 : External interrupt 1. - PT0 : Timer 0. - PX0 : External interrupt 0. - 0 = Low priority. - 1 = High priority. IP: Interrupt Priority Register ----- ----- ----- PS PT1 PX1 PT0 PX0

45. ·Controlled Power Reduction ·Idle State ·Power down state ·Power savings in CMOS ports · General purpose software flags · Higher speed versions in 80C51 (up to 30MHz) · Static versions in development 80C51(CMOS) vs. 8051(NMOS)

46. - POWER DOWN OPERATION Setting PD bit stops oscillator. RAM contents are saved. Exit via Reset. Some (newer) 80C51 derivatives allow Power-Down wakeup via Interrupt. PCON : Power Control Register SMOD ---- ---- ---- GF1 GF0 PD IDL

47. - IDLE MODE OPERATION Setting IDL gates clocks off, leaves oscillator running. All register and RAM contents are saved. Interrupt sources remain active: Serial interface. External interrupts. Timers. Exit with any enabled interrupt or Reset. - GF0, GF1 are general purpose software flags. - SMOD serial interface control bit. Doubles baud rate in modes 1,2, and 3. - Only SMOD available on NMOS parts. PCON : Power Control Register

48. Example : for 80C51 at Vcc = 5V. Mode / Freq. 0.5 MHz 16 MHz Operating 2.2 mA 20.5 mA Idle 0.9 mA 5.0 mA Power Down 50 uA 50 uA Power Consumption