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Pedram A. Riahi Mehdi B. Tahoori Zainalabedin Navabi Fabrizio Lombardi

Intellectual Property (IP) Core-based System-on-Chip (SoC) Testing using Hardware Description Languages’ (HDLs) Procedural Language Interface (PLI). Pedram A. Riahi Mehdi B. Tahoori Zainalabedin Navabi Fabrizio Lombardi Electrical and Computer Engineering Department

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Pedram A. Riahi Mehdi B. Tahoori Zainalabedin Navabi Fabrizio Lombardi

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  1. Intellectual Property (IP) Core-based System-on-Chip (SoC) Testing using Hardware Description Languages’ (HDLs) Procedural Language Interface (PLI) Pedram A. Riahi Mehdi B. Tahoori Zainalabedin Navabi Fabrizio Lombardi Electrical and Computer Engineering Department Northeastern University Weekly Test Seminars

  2. Introduction • System-on-Chip (SoC) • SoC Testing • Present Solutions • Hardware Description Languages (HDLs) • SoC Testing using PLI • Benchmarks • Conclusion and Future Works Weekly Test Seminars

  3. System-on-Chip (SoC) • Complex Functional Blocks • System-on-Board • Core: • μP/μC • DSP • Memory • Function-Specific • Logic Element • Communication Peripheral • Analog Device Weekly Test Seminars

  4. System-on-Chip (SoC) • Reusable Cores • Core Types: • Soft (Synthesizable) • Firm • Hard • Intellectual Property (IP) • In-house cores Weekly Test Seminars

  5. SoC Testing • Traditional Test Methods • Core-Level Testing • Design For Test (DFT) • Automatic Test Pattern Generation (ATPG) • Chip-Level Testing • Justifying Test Sequences • Propagating Test Response Weekly Test Seminars

  6. Present Solutions • Core-Level Testing • System Chip’s Functional Test • Direct Access (I/O Muxing) • Local Boundary-Scan or Collar Register • Full-Scan / Built-in-Self-Test (BIST) • Proprietary Solution • Chip-Level Testing Weekly Test Seminars

  7. Present Solutions • Full-Scan / Boundary-Scan (FScan-BScan) Full- or Partial-Isolating Rings / Control Points FScan-BScan Weekly Test Seminars

  8. Present Solutions • Full-Scan / Test Bus (FScan-TBus) • Test Bus / Boundary-Scan Chain Weekly Test Seminars

  9. Present Solutions • Binary Decision Diagram (BDD) • Partial Netlist / Partial Boundary Scan Weekly Test Seminars

  10. Present Solutions • Core Transparency FPath HScan Weekly Test Seminars

  11. Present Solutions • IEEE P1500 • BIST • Chip-Level Testing • Parallel Direct Access • Serial Scan Access • Functional Access Weekly Test Seminars

  12. Hardware Description Languages (HDLs) • VHDL • Verilog • Procedural Interfaces: • VHPI • VPI • Cadence NC-Verilog • C Platform Weekly Test Seminars

  13. SoC Testing with VPI • VPI-based Test Environment • VPI-based Fault Simulation • Single Stuck-at Fault • Serial • VPI-based Test Generation • Random Pattern Weekly Test Seminars

  14. Fault Simulationwith VPI • Flat (nonMixed-Level) • Mixed-Level Wrapper Structure Weekly Test Seminars

  15. Fault Simulation with VPI • Proposed VPI Tasks for Serial Fault Simulation • $faultlist • Node Type: reg, net • Node Name: ~.module_name/node_name • Stuck-at: sa0, sa1 • Not Injected • Injected but not Detected • Partially Detected • Detected • $faultinjection, $faultrelease • $preinjection, $postrelease • $updatefaultlist Weekly Test Seminars

  16. Test Generation with VPI • Proposed VPI Tasks for Directed Random Pattern Test Generation • $faultcoverage • $morefault • $decide • $readstatus, $restorestatus • Status: 0, 1, X, Z • $randomvector • $saveoutput, $compareoutput • $savevector Weekly Test Seminars

  17. Test Generation with VPI • Initialization doread := true; $faultlist; while !($faultcoverage(coverage) satisfied) { if (doread) $readstatus; $randomvector(depth); $readmem; for (all vectors) { Apply Vector; $saveoutput; } … Fault Injection and Simulation … Decide } • Red is just required for Sequential Designs Weekly Test Seminars

  18. Test Generation with VPI • Fault Injection and Simulation Lindex := 0; while ($morefault) { $restorestatus; $faultinjection(1); flag := true; for (all vectors and flag) { Apply Vector; if ($compareoutput == detected) { $updatefaultlistone(1); flag := false; Lindex := Largest index; } $faultinjection(2); } Weekly Test Seminars

  19. Test Generation with VPI • Decide if ($decide(limit) == GOOD) { $savevector; $updatefaultlist(2); if (Lindex > depth) { $restorestatus; for (all vectors that index < Lindex) Apply Vector; } doread := true; } else { $restorestatus; $updatefaultlist(3); doread := false; } Weekly Test Seminars

  20. Benchmarks • Flat Serial Fault Simulation (PARWAN: WRTLT’02, ISCAS85-89: NATW’03) • Behavioral Operations vs. Primitive Gates and Mixed Level Serial Fault Simulation (PARWAN: ESA’03, ISCAS85: ATS’03) • Higher Level Behavioral Description and Directed Random Pattern Test Generation (ITC’04) • Generating a Series of SoC Benchmarks Weekly Test Seminars

  21. Conclusion and Future Works • A Methodology for SoC IP Core Testing • Mixed-Level Serial Fault Simulation • Directed Random Pattern Test Generation • Eliminating Traditional Hardware Wrappers • Delay and Area Overheads • VPI-based Deductive or Concurrent Fault Simulation • VPI-based PODEM and D-Algorithm • Mixed-Mode SoC Testing Weekly Test Seminars

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