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A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis for Data Transmission over 75 W Coaxial Cable

A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis for Data Transmission over 75 W Coaxial Cable. Ricardo A. Aroca & Sorin P. Voinigescu Edward S. Rogers, Sr. Dept. of Electrical & Comp. Eng., University of Toronto, Toronto, ON M5S 3G4, Canada. Outline. Motivation

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A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis for Data Transmission over 75 W Coaxial Cable

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  1. A Large Swing, 40-Gb/s SiGe BiCMOS Driver with Adjustable Pre-Emphasis forData Transmission over 75W Coaxial Cable Ricardo A. Aroca & Sorin P. Voinigescu Edward S. Rogers, Sr. Dept. of Electrical & Comp. Eng., University of Toronto, Toronto, ON M5S 3G4, Canada

  2. Outline • Motivation • Driver Specifications • Driver Architecture and Design • Measurements • Transmission Experiment • Conclusions

  3. TX/RX IC Belden 1694A Motivation • Transport 40-Gb/s over existing coaxial cable infrastructure • Transceiver IC must be low-cost, highly integrated, and capable of equalizing up to 50dB of channel losses

  4. Line driver • Focus on the TX, RX in development • TX requires amplitude control and pre-emphasis control • Place as much equalization into the TX to ease the RX specs Transceiver Architecture Transmitserializer and40-G PLL Line driver FFE DFE 40-GHzclock 40 Gb/s@ 5V 40 Gb/s @ 1 – 1.8V TimingRecovery 40-GHzclock

  5. CMOS 40-Gb/s, 75W Driver Specifications

  6. HV-HBT, BVceo=3.5V fMAX = 100GHz fT = 75GHz JpkfT= 2.5mA/mm2 HV-HBT Production Technology Jazz HX 0.2mm SiGe BiCMOS 0.18mm n-MOSFET fMAX = 75GHz fT = 50GHz JpkfT = 0.3mA/mm NMOS

  7. 75W 75W Microstrip T-Line Sections 8V 8V OUTP Pre-Driver INP 5V 75W 3 4 6 7 1 2 5 INN 75W 8V OUTN 8V AMP 75W Amp & Pre-Emphasis Itail CNTRL DCC Distributed Architecture Design • IOUT = 5Vpp/(75W//75W) = 133mA  19mA/section • Must fully switch the DA  predriver: 1.5Vpp, 40mA • Gain of predriver = 1.5/0.2 = 18dB, 3dB/stage  6 stages • Distributed pre-emphasis is implemented for the first time • Amplitude control is implemented in both the DA and predriver

  8. T-line section T-line compensation ~5V ~5V fT=75GHz fMAX=100GHz HV-HBT IOFF C C IMAIN R R VPRE VPRE IPRE DA Section Schematic RC-HPF & Digital HBT fT=160GHz, fMAX=160GHz 0.18mm n-MOSFETs fT=50GHz, fMAX=75GHz

  9. T-line section T-line compensation ~5V ~5V IOFF C C IMAIN R R IT VPRE VPRE IPRE IT=IMAIN+IPRE DA Section Schematic • IT is variable, for amplitude control at different pre-emphasis settings • IOFF adjusts to ensure current through HV-HBT is constant

  10. Driver Microphotograph 1.2mm Predriver Distributed Amplifier 2.5mm

  11. 22GHz 10dB S-parameter Measurements vs. Simulations: 10dB of Amplitude Control

  12. 25dB S-Parameter Measurements vs. Simulations: 25dB of Pre-Emphasis Control

  13. 25oC 3Vpp 1Vpp 125oC • Input: 200mVpp, 4x(231-1 PRBS) • 2ps RMS jitter (1khits) • ~11ps rise/fall times 1.9Vpp 40-Gb/s Eyes @ 25oC and 125oC

  14. 25oC 1.3Vpp 1Vpp 2Vpp 125oC • Input: 200mVpp, 4x(231-1 PRBS) • 200-400% pre-emphasis 40-Gb/s Pre-Emphasis @ 25oC and 125oC

  15. Maximum Output Amplitude @ 38Gb/s 3.6Vpp per side in a 50W load, 10.5ps rise time, 2.2ps RMS jitter (1.17khits)

  16. 40-Gb/s Driver Performance in 50W

  17. 40-Gb/s, 50W Driver Comparison *LD – Lumped predriver followed by a distributed amplifier *[ ] – Reference numbers refer to those cited in the paper

  18. T T To Remote Sampling Head (RSH) Transmission Experiment over 10m, 30m and 40m of Belden Coaxial Cable INPUT TO CHANNEL BIAS 4x231-1 PRBS K-SMA-BNC RSH Source RSH BIAS 10m,30m,40m coax AFTER CHANNEL

  19. CHANNEL INPUT TO CHANNEL AFTER CHANNEL Equalized Channel Response Range of all possible equalized channel responses

  20. -24dB 50mVpp 10-Gb/s over 40m Coax No Pre-emphasis With Pre-emphasis

  21. -23dB 40- & 38-Gb/s over 10m Coax No Pre-emphasis 200mVpp 200mVpp Pre-emphasis @40Gb/s Pre-emphasis @38Gb/s

  22. Conclusions • Large swing, fully-differential 40-Gb/s SiGe BiCMOS cable driver with adjustable pre-emphasis has been presented. • Key features include: • Distributed pre-emphasis technique • MOS-HV-HBT cascode topology • Transmission experiments over Belden 1694A coax: • equalization of -24dB of loss at 5GHz • equalization of -22dB at 19GHz • Experimental results indicate that this driver could also be used as a 50W EAM driver operating at 40 Gb/s.

  23. Acknowledgements • Jazz Semiconductor and Marco Racanelli for fabrication • Gennum Corporation and NSERC for funding • Jaro Pristupa for CAD support

  24. Backup Slides

  25. Coax RSH RSH DUT To Remote Sampling Head (RSH) Transmission Experiment over 10m, 30m and 40m of Belden Coaxial Cable Source

  26. -17.7dB 30-Gb/s 38- & 30-Gb/s over 10m Coax Cable

  27. -29dB 20-Gb/s over 30m Coax Cable

  28. Measurement Bottlenecks • 75W cable driver to be measured in a 50W environment Eventual packaging will solve this problem • How will S21 and S22 change when driving a 75W load when compared to the 50W measurement? S21 and S22 will improve in theory • How can we verify the maximum swing to be expected in a 75W environment? Theoretically the swing driving 75W should be 1.25 times the swing driving 50W

  29. Driver Output Impedance: Measurements vs. Simulations

  30. DCC Control @ 40- and 30-Gb/s

  31. System Integration ? Low cost High-speed (40Gb/s) Output swing (5Vpp per side) ? Reliability over temperature SiGe BiCMOS is the best option 40-Gb/s Retimer in 90nm CMOS – need 65nm for margin T. Chalvatzis, JSSC07 Choice of Technology CMOS 90/65nm SiGe BiCMOS III-V Considerations

  32. Vdd Vdd 75W 75W IT = 5Vpp / 37.5W = 133mA Line driver 75W 75W Vdd Vdd Initial Driver Design • Driving a 75W coax cable with 5Vpp per side requires digital switching of ~133mA • For reliable operation under large output voltage swings, high voltage HBTs (HV-HBT) are required at the output node • BVCEO=3.5V • fT = 75GHz • fMAX = 100GHz • RC time constant analysis, when the HV-HBT is biased at 0.75*JpkfT, results in a -3dB bandwidth of ~10GHz, • Lumped toplogy is not an option therefore pointing to a distributed architecture (at least for the output stage)

  33. ~3.3V ~3.3V 300mV 400mV 800mV 1V 1.2V Output Swing per side: ~3.3V ~3.3V ~3.3V 50W 1.1 - 1.8V INP Small Input Device to minimize capacitance andimprove input matching without EFs 5mA 5mA 3mA 10mA 20mA 40mA 60W INN Vdd Vdd DCC DCC current 50W Amplitude Control 75W 75W Offset Control 600W 10mA Lumped Predriver Architecture • BiCMOS cascode used in the final two stages for stability • Topology is ideal for impelmenting amplitude control Input DC 1.1V - 1.8V

  34. ~5V ~3.3V ~3.3V 8 x 5.46mm HV-HBT 8 x 5.46mm Digital 2mm x 66 L=0.18mm 40mA Output Stage 75W 75W

  35. T-line section • Distributed T-line inductors designed to absorb the load capacitance from the DA stage • minimize the impact on Z0, S21, and phase distortion T-Line Compensation

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