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ECE 448 Lecture 1 6

ECE 448 Lecture 1 6. Bit Counter Shift-and-Add Multiplier. Required reading. S. Brown and Z. Vranesic , Fundamentals of Digital Logic with VHDL Design Chapter 10.2.1 , A Bit-Counting-Circuit Chapter 10.2.2, ASM Chart Implied Timing Information

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ECE 448 Lecture 1 6

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  1. ECE 448 Lecture 16 Bit CounterShift-and-Add Multiplier ECE 448 – FPGA and ASIC Design with VHDL

  2. Required reading • S. Brown and Z. Vranesic,Fundamentals of Digital Logic with VHDL Design • Chapter 10.2.1, A Bit-Counting-Circuit • Chapter 10.2.2, ASM Chart Implied Timing • Information • Chapter 10.2.3, Shift-and-Add Multiplier ECE 448 – FPGA and ASIC Design with VHDL

  3. Bit Counter ECE 448 – FPGA and ASIC Design with VHDL

  4. Pseudo-code for the bit counter B = 0; while A≠0 do if a0 = 1 then B = B + 1; end if; Right-shift A; end while ; ECE 448 – FPGA and ASIC Design with VHDL

  5. ASM chart of the bit counter Reset S1 ¬ B 0 Load A 0 0 1 s s 1 S2 S3 Shift right A Done 1 ¬ A = 0 ? B B + 1 0 0 a 0 1 ECE 448 – FPGA and ASIC Design with VHDL

  6. Expected behavior of the bit counter ECE 448 – FPGA and ASIC Design with VHDL

  7. Datapath of the bit counter 0 Data log n n 2 w 0 LB L L Counter LA EB E Shift E EA Clock log n A 2 n z B a 0 ECE 448 – FPGA and ASIC Design with VHDL

  8. ASM chart for the bit counter control circuit ECE 448 – FPGA and ASIC Design with VHDL

  9. VHDL code of the bit counter (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY work ; USE work.components.shiftrne ; ENTITY bitcount IS PORT(Clock, Resetn : IN STD_LOGIC ; LA, s : IN STD_LOGIC ; Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; B : BUFFER INTEGER RANGE 0 to 8 ; Done : OUT STD_LOGIC ) ; END bitcount ; ECE 448 – FPGA and ASIC Design with VHDL

  10. VHDL code of the bit counter (2) ARCHITECTURE Behavior OF bitcount IS TYPE State_type IS ( S1, S2, S3 ) ; SIGNAL y : State_type ; SIGNAL A : STD_LOGIC_VECTOR(7 DOWNTO 0) ; SIGNAL z, EA, LB, EB, low : STD_LOGIC ; BEGIN FSM_transitions: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= S1 ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN S1 => IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ; WHEN S2 => IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ; WHEN S3 => IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ; END CASE ; END IF ; END PROCESS ; ECE 448 – FPGA and ASIC Design with VHDL

  11. VHDL code of the bit counter (3) FSM_outputs: PROCESS ( y, A(0) ) BEGIN EA <= '0' ; LB <= '0' ; EB <= '0' ; Done <= '0' ; CASE y IS WHEN S1 => LB <= '1' WHEN S2 => EA <= '1' ; IF A(0) = '1' THEN EB <= '1' ; ELSE EB <= '0' ; END IF ; WHEN S3 => Done <= '1' ; END CASE ; END PROCESS ; ECE 448 – FPGA and ASIC Design with VHDL

  12. VHDL code of the bit counter (4) -- The datapath circuit is described below upcount: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN B <= 0 ; ELSIF (Clock'EVENT AND Clock = '1') THEN IF LB = '1' THEN B <= 0 ; ELSEIF EB = '1' THEN B <= B + 1 ; END IF ; END IF; END PROCESS; ECE 448 – FPGA and ASIC Design with VHDL

  13. VHDL code of the bit counter (5) low <= '0' ; ShiftA: shiftrne GENERIC MAP ( N => 8 ) PORT MAP ( Data, LA, EA, low, Clock, A ) ; z <= '1' WHEN A = "00000000" ELSE '0' ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

  14. Shift-and-Add Multiplier ECE 448 – FPGA and ASIC Design with VHDL

  15. An algorithm for multiplication Decimal Binary 13 1 1 0 1 Multiplicand 11 1 0 1 1 Multiplier ´ ´ 13 1101 13 1 1 0 1 0 0 0 0 143 1 1 0 1 1 0 001111 Product (a) Manual method P = 0 ; – i = 0 n 1 for to do b = 1 if then i P = P + A ; end if; A Left-shift ; end for; (b) Pseudo-code ECE 448 – FPGA and ASIC Design with VHDL

  16. ASM chart for the multiplier Reset S1 ¬ P 0 Load A Load B 0 0 1 s s 1 S2 S3 Shift left A , Shift right B Done 1 ¬ B = 0 ? P P + A 0 0 b 0 1 ECE 448 – FPGA and ASIC Design with VHDL

  17. Expected behavior of the multiplier ECE 448 – FPGA and ASIC Design with VHDL

  18. Datapath for the multiplier LA 0 DataA LB DataB n n n L L Shift-left Shift-right EA EB E E register register A B Clock n 2n + z b Sum 0 0 2n 2n 1 0 Psel 2n DataP EP E Register 2n P ECE 448 – FPGA and ASIC Design with VHDL

  19. ASM chart for the multiplier control circuit ECE 448 – FPGA and ASIC Design with VHDL

  20. VHDL code of multiplier circuit (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; USE work.components.all ; ENTITY multiply IS GENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ; PORT ( Clock : IN STD_LOGIC ; Resetn : IN STD_LOGIC ; LA, LB, s : IN STD_LOGIC ; DataA : IN STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; DataB : IN STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; P : BUFFER STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; Done : OUT STD_LOGIC ) ; END multiply ; ECE 448 – FPGA and ASIC Design with VHDL

  21. VHDL code of multiplier circuit (2) ARCHITECTURE Behavior OF multiply IS TYPE State_type IS ( S1, S2, S3 ) ; SIGNAL y : State_type ; SIGNAL Psel, z, EA, EB, EP, Zero : STD_LOGIC ; SIGNAL B, N_Zeros : STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; SIGNAL A, Ain, DataP, Sum : STD_LOGIC_VECTOR(NN–1 DOWNTO 0) ; BEGIN FSM_transitions: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0’ THEN y <= S1 ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN S1 => IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ; WHEN S2 => IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ; WHEN S3 => IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ; END CASE ; END IF ; END PROCESS ; ECE 448 – FPGA and ASIC Design with VHDL

  22. VHDL code of multiplier circuit (3) FSM_outputs: PROCESS ( y, s, B(0) ) BEGIN EP <= '0' ; EA <= '0' ; EB <= '0' ; Done <= '0' ; Psel <= '0'; CASE y IS WHEN S1 => EP <= '1‘ ; WHEN S2 => EA <= '1' ; EB <= '1' ; Psel <= '1‘ ; IF B(0) = '1' THEN EP <= '1' ; ELSE EP <= '0' ; END IF ; WHEN S3 => Done <= '1‘ ; END CASE ; END PROCESS ; ECE 448 – FPGA and ASIC Design with VHDL

  23. VHDL code of multiplier circuit (4) - - Define the datapath circuit Zero <= '0' ; N_Zeros <= (OTHERS => '0' ) ; Ain <= N_Zeros & DataA ; ShiftA: shiftlne GENERIC MAP ( N => NN ) PORT MAP ( Ain, LA, EA, Zero, Clock, A ) ; ShiftB: shiftrne GENERIC MAP ( N => N ) PORT MAP ( DataB, LB, EB, Zero, Clock, B ) ; z <= '1' WHEN B = N_Zeros ELSE '0' ; Sum <= A + P ; - - Define the 2n 2-to-1 multiplexers for DataP GenMUX: FOR i IN 0 TO NN–1 GENERATE Muxi: mux2to1 PORT MAP ( Zero, Sum(i), Psel, DataP(i) ) ; END GENERATE; RegP: regne GENERIC MAP ( N => NN ) PORT MAP ( DataP, Resetn, EP, Clock, P ) ; END Behavior ; ECE 448 – FPGA and ASIC Design with VHDL

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