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EE/MatE 167

EE/MatE 167. MOSFET Review. MOSFET. Metal Insulator Semiconductor (MIS) transistor Insulated Gate Field Effect Transistor (IGFET) Majority Carrier Device. Ideal MOS Capacitor. In this section we will discuss an ideal case and then add in “real surfaces” later.

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EE/MatE 167

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  1. EE/MatE 167 MOSFET Review MatE/EE 167

  2. MOSFET • Metal Insulator Semiconductor (MIS) transistor • Insulated Gate Field Effect Transistor (IGFET) • Majority Carrier Device. MatE/EE 167

  3. Ideal MOS Capacitor • In this section we will discuss an ideal case and then add in “real surfaces” later. • Modified work functions are necessary • Metal-Oxide interface qfm • Semiconductor-Oxide interface qfs MatE/EE 167

  4. Band Diagram of a MOS Capacitor MatE/EE 167

  5. Band Diagram of a MOS Capacitor MatE/EE 167

  6. Band Diagram of a MOS Capacitor MatE/EE 167

  7. Band Diagram of a MOS Capacitor MatE/EE 167

  8. Capacitance MatE/EE 167

  9. Basic MOSFET operation • n-channel • A positive voltage is applied to the gate thus attracting electrons which form a channel between the two n+ source and drain regions • p-channel • A negative voltage is applied to the gate thus attracting hole which form a channel between the two p+ source and drain regions MatE/EE 167

  10. Basic MOSFET operation • n-channel • Requires a gate voltage more positive than VT to create an electron channel. • p-channel • Requires a gate voltage more negative than VT to create an electron channel. MatE/EE 167

  11. Basic MOSFET operation MatE/EE 167

  12. Basic MOSFET operation • depletion mode • Already have a channel with zero gate voltage and a negative voltage is required to turn it off. • enhancement mode • Requires a gate voltage larger than VT to induce a channel. MatE/EE 167

  13. Basic MOSFET operation • PMOS • a p-type channel is created in a n-type substrate. • NMOS • an n-type channel is created in a p-type substrate. MatE/EE 167

  14. Basic MOSFET operation MatE/EE 167

  15. Examples • Solve Example 8-1 except Na=1x1017cm-3 • Solve Example 8-2 except use a 50Å SiO2 layer. MatE/EE 167

  16. Effects of Real Surfaces • Work Function Difference: • Doping level changes (fms= fm-fs) • Always negative • To take into account band bends down (can even cause a channel to exist). • Interface Charge: • Qm (Mobile ionic), Qot (Oxide trapped), Qf (Oxide fixed), Qit (Interface trap) MatE/EE 167

  17. Work Function Difference MatE/EE 167

  18. Effects of Real Surfaces MatE/EE 167

  19. Effects of Real Surfaces MatE/EE 167

  20. Real Surfaces • Interface Charge: • Qm (Mobile ionic) Sodium atoms move around under electric field • Qot (Oxide trapped) Imperfections in SiO2 cause charge to be trapped • Qf (Oxide fixed) Ionic silicon left over from oxidation process. • Qit (Interface trap) Charge due to abrupt interface of SiO2 and Si. MatE/EE 167

  21. Threshold Voltage (Al Gate) MatE/EE 167

  22. Threshold Voltage MatE/EE 167

  23. The MOS Field-Effect Transistor MatE/EE 167

  24. The MOS Field-Effect Transistor MatE/EE 167

  25. The MOS Field-Effect Transistor MatE/EE 167

  26. Control of Threshold Voltage • Silicon gate technology • Fms is reduce by using poly-silicon as the gate • Poly-silicon must be heavily doped • Fms is now just the difference in Fermi levels of the two silicon regions. • Poly-silicon is also more process friendly (It can withstand higher temperatures than Al) MatE/EE 167

  27. Control of Threshold Voltage • Control of Ci • We would like a small VT under the gate but elsewhere we would like a large VT to prevent channels from forming between transistors. • Smaller Ci, leads to a smaller threshold. MatE/EE 167

  28. Control of Threshold Voltage • Ion Implantation • B ions can be implanted in a two dimensional sheet just below the oxide layer. These ions are negatively charged and can be used to offset Qd. Dose typically 10 seconds. MatE/EE 167

  29. Control of Threshold Voltage • Control Qi • Grow the SiO2 layer on {100} oriented wafers • Less dangling bonds • Slower growth rate leads to higher quality layer • HCl in oxygen reduces sodium in SiO2 MatE/EE 167

  30. Substrate Bias Effect • We add a contact to the body (Normally the source and body are ties together at ground) MatE/EE 167

  31. What is “Pinch off” • For a given VG, you have a maximum amount of current you can flow through the channel (regardless of VD). • When VD=VG-VT the channel is flowing as much current as it can so we call it pinched off (even though current continues to flow). MatE/EE 167

  32. MatE/EE 167

  33. Capacitance Effects and Self-Aligned Transistors • There are several capacitances that limit the high frequency operation of MOSFETS. • Non-Self Aligned is the worst case due to the metal overlapping the source and drain regions. MatE/EE 167

  34. Capacitance Effects and Self-Aligned Transistors • Self aligned gates with an Al gate (plus an ion-implantation) offer reduce capacitance • However: Wafer needs to be annealed, and the annealing temp has to be less than 500 oC. MatE/EE 167

  35. Capacitance Effects and Self-Aligned Transistors • Poly Silicon Process: • Self aligned, and can withstand higher temps. MatE/EE 167

  36. Short Channel Effects • There is a depletion region near the Drain body interface that creeps under the gate. • This makes the actual channel length smaller than the length of the gate. If this depletion width is similar in size to the gate length, then it will affect the transistors IV curve. • The larger VD the larger the depletion region and the smaller the channel length: This leads to increased current (looks like the early effect) MatE/EE 167

  37. Short Channel Effects • The depletion regions of the two junctions can meet if the channel length is small enough. At this point the current is not controlled by the gate voltage but by VD2/L3. • Sub threshold current: • Some electrons are flowing before a channel is completely induced, and the is diffusion of electron from source to drain that can make it impossible to turn the device off. • Doping the source and drain heavily near the contacts and lightly near the gate can alleviate much of this problem. This lowers the electric field thus less electrons can be injected below threshold. • (Why? This is a diode question.) MatE/EE 167

  38. Short Channel Effects MatE/EE 167

  39. Short Channel Effects MatE/EE 167

  40. MOS Regions of Operation MatE/EE 167

  41. Small Signal Model of MOSFET MatE/EE 167

  42. MOSFET fT MatE/EE 167

  43. MOSFET fT MatE/EE 167

  44. High Frequency Performance of MOSFETs MatE/EE 167

  45. CMOS INVERTER MatE/EE 167

  46. CMOS INVERTER MatE/EE 167

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