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十 位元 SAR ADC 設計

十 位元 SAR ADC 設計. 謝岳霖. 大綱. SAR ADC 架構及原理 SAR ADC 各區塊設計. SAR ADC 架構及原理. Vin. S/H. comp. vcomp. start. clk. vdac. b1~b10. start. clk. ……. SAR Logic. box. DAC Array. stop. …. b1~b10. 此電路架構是採用一個比較器，一個電容陣列的 DAC 轉換器、一組 SAR Logic 控制電路所組成的 SAR ADC. Vin. S/H. comp. vcomp. start.

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十 位元 SAR ADC 設計

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  1. 十位元SARADC設計 謝岳霖

  2. 大綱 • SARADC架構及原理 • SARADC各區塊設計

  3. SARADC架構及原理 Vin S/H comp vcomp start clk vdac b1~b10 start clk ……. SAR Logic box DAC Array stop ….. b1~b10 此電路架構是採用一個比較器，一個電容陣列的DAC轉換器、一組SAR Logic控制電路所組成的SARADC

  4. Vin S/H comp vcomp start clk vdac b1~b10 start clk ……. SAR Logic box DAC Array stop ….. b1~b10 轉換原理：SARADC在開始的時候會讓SARlogic一開始先全部輸出設為1 接著先將值給DAC轉換出DAC值 轉出的DAC值再與vin輸入做比較 再將比較器的輸出結果給SARlogic 比較十次之後結束比較

  5. SARADC各區塊設計 Vin S/H comp vcomp start clk vdac b1~b10 start clk ……. SAR Logic box DAC Array stop ….. b1~b10 SARADC各區塊包含： sample_hold(S/H)、比較器、電容式DAC(DACArray)、SARLogic、頻率控制電路(box)

  6. sample_hold(S/H) 此sample hold是採用拔靴式開關做成。

  7. sample_hold(S/H)LAYOUT

  8. sample_hold(S/H)模擬結果

  9. 比較器架構圖

  10. 啟動&偏壓電路

  11. 比較器layout 啟動&偏壓電路

  12. 比較器模擬結果

  13. 電容式DAC架構圖 vdac b1 b2 b3 b4 b5 b6 b7 b8 b9 b10

  14. 電容式DAC模擬結果

  15. 電容式DAC

  16. SAR_logic架構圖

  17. SAR_logic模擬結果 當comp輸入dc HI時，輸出結果會如下圖

  18. SAR_logic Layout

  19. 10位元SAR ADC完整Layout圖

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