Transmitter for Quantum Encryption System

1. High Speed Digital Systems Laboratory Transmitter for Quantum Encryption System Midterm presentation Spring 2006 Supervisor: Yossi Hipsh Performed by: Asaf Holzer Edward Shifman

2. Project Objectives • The transmitter module is part of a complex system, which • purpose is to send a digital code, which will later be used as • key for encrypting and decrypting information. • Our goal is to produce an electrical pulse which is ~0.5ns • wide and its magnitude is 4v. The purpose of this pulse is to • activate the laser diode.

3. The Overall System Block Diagram Computer (Controller) Computer + Counter Synchronization Transmitter Reciever Interfrometers, etc.

4. Original Plan Pulse trigger monostable D.D.L TTL 2 ECL ECL Programmable Delay Chip 1:2 And Gate ECL Programmable Delay Chip 1:2 Long fiber Bal_UN Bal_UN Gain Gain P_Quant P_Sync

5. Original Plan – continued… Pulse trigger monostable D.D.L TTL 2 ECL ECL Programmable Delay Chip 1:2 And Gate ECL Programmable Delay Chip 1:2 Long fiber Bal_UN Bal_UN Gain Gain Ref P_Stab

6. The ECL Programmable Delay Chip SY100EP195V (by Micrel) : Has 10 control bits, so we can delay the pulse by 2-12ns. (Delay range = 210 x step_delay = 210 x 10ps = 10ns) Conclusion: We can manage without the TTL delay (and the long fiber delay).

7. Some more advances In order to improve the module’s performance we decided to use ECL technology from the very beginning of the pulse module, so we put the TTL-ECL device at the beginning. We replaced the components so they will operate in 3.3 voltage level.

8. Plan #2 ECL Prog. Delay Chip Pulse trigger ECL Prog. Delay Chip 1:2 And Gate ECL Prog. Delay Chip … TTL 2 ECL Bal_UN P_Sync monostable Gain … 1:4 P_Sync P_Quant … Ref

9. The Monostable (ECL) MC100EP31 Flip Flop S Q ECL Prog. Delay Chip 1 1:4 (ECL) D R Q ECL Prog. Delay Chip 2 CLK ECL Prog. Delay Chip 3 MC100EP31 Characteristics:

10. The Monostable Timing Diagram Data t CLK ts t Reset t Q tR-Q tclk-Q t Q Min. Pulse width: 530ps 130ps 400ps

11. Final Plan Computer – LabView trig stab_en sync_ctrl counter 1:4 (TTL) sel sel Mux Mux 1:4 (TTL) TTL-ECL TTL-ECL TTL-ECL Pulse-Module Pulse-Module Pulse-Module P_Quant P_Stab P_Sync detector ref ref

12. Inputs & Outputs Voltage Source trig. stab_en sync_ctrl counter Ref (2) Ref (1) P_Stab P_Quant (0.5 nsec) P_Sync

13. Final Plan – Pulse Module 10ns Bal_UN Gain 3ns 0.5ns monostable monostable 1:2 Bal_UN Gain And Gate ref Plan B

14. Final Plan – Pulse Module 3ns S Flip Flop Q 1:4 (ECL) D Q CLK ECL Prog. Delay Chip 1 R ECL Prog. Delay Chip 2 0.5ns S Flip Flop Q 1:4 (ECL) D ECL Prog. Delay Chip 3 CLK ECL Prog. Delay Chip 4 R Q ECL Prog. Delay Chip 5 And Gate 0.5ns

15. Final Plan – Timing Delays Time Table: Delay 1: 6.0ns Delay 2: 3.0ns Delay 3: 3.0ns 3.0ns Delay 4: 3.84ns 3.5ns Delay 5: 3.5ns 6.35ns Plan A Plan B

16. The Bal-UN OUT + IN 140Ω 140Ω - 68Ω 68Ω 68Ω 68Ω 150Ω 100nF 1nF 150Ω 1nF 100nF

17. Component List (*) To be approved by the project supervisor

18. The Transmitter Block Diagram FPGA Spartan III Bus1 Bus2 PulseModule 3 PulseModule 1 PulseModule 2 P_Sync P_Quant P_Stab

19. Achieved so far: • Finished final design including pulse module with improvements • (discussed before) • Components have been chosen (some still waiting to be approved by • the supervisor). • Currently working on Orcad scheme.

20. Yet to do • Approving new design by supervisor, including components. • Finishing Orcad scheme. • Ordering components. • Wiring-up the circuit. • Writing VHDL for the FPGA. • Testing the wired-up circuit.