Section 10: Advanced Topics

1. Section 10: Advanced Topics M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

2. Multi-Level Logic Synthesis M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

3. Objective The objective in multi-level logic synthesis is to minimize the cost under a given time-constraint (reflected as number of levels) or to perform an area-time tradeoff.

4. Issues in Multi-level Logic Synthesis The main issue is to factorise the multiple outputs (or sub-expressions in a single output function) with a view to extract the common sub-expressions.

5. Common Subexpression Extraction y2 y1 y1 y2 x1 x2 xn

6. Example y1 = ac + b’c + de y2 = ae’ + b’e’ + e’f t1 = (a + b’) y1 = t1c + de y2 = t1e’ + e’f

7. Binary Decision Diagram (BDD) For representation and manipulation of boolean functions, BDDs are used. For a given ordering of variables, the BDD representation for a function is canonical and for this reduced and ordered BDDs called ROBDDs are used.

8. Example: BDD y1 = a + b’c a 1 0 b b 1 0 1 0 c c c c 1 0 1 1 0 0 1 1

9. Example: ROBDD a 0 b 1 1 0 c 1 0 0 1

10. Low Power Design M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

11. Why Low Power Design ? The need for low power design originates from two different considerations • Mobile applications: Battery life is a critical factor in making a product commercially successful • High-frequency VLSI circuits where low power dissipation is critical for circuit functionality and reliability

12. Technology • Universally the technology of choice for low power is CMOS • A major component of power consumption is the switching power with leakage etc. contributing insignificantly • The power dissipated by a gate is given by 0.5  Cload  Vdd2  E(transitions)/ Tcyc

13. Issues in Low Power Design • Accurate estimations of power consumption at higher levels of design abstractions • Power reducing design transformations • Uniform distribution of power in the chip • Packaging for effective power dissipation to maintain “cool” operations

14. Power Estimation Power can be estimated by simulating the behavior at different levels. • Transistor level • Gate level • RTL module level • Software power estimation • Architecture level

15. Design Transformations • Critical path reduction • Reducing the number of operations • Reducing the transition activity • Reducing the interconnect capacitance • Operation substitution • Bit-width optimization

16. Critical Path Reduction • Reducing the critical path implies larger acceptable delays which in turn means a lower Vdd Delay Vdd

17. Transition Activity Reduction • Reduction in variation in path lengths • Coding of numbers • Coding of states and instructions

18. Transition Activity Reduction (contd.) d a b c b a + + + c + + d +

19. Operation Substitution • Some operations are very expensive in terms of power and in case it can be replaced by equivalent operations its is preferable e.g multiply by shift and add especially for multiplications with a constant

20. Behavioral Synthesis M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

21. Why Behavioral Synthesis ? There is urgent need for pushing up the abstraction level at which the design can start. The reasons for this are: • As the complexity increases, this is the only way to reduce the design turn around time • An algorithmic description of the functionality is far easier to write than designing hardware

22. Steps in Behavioral Synthesis • Data path synthesis • Scheduling • Resource allocation (where resources include functional units, storage units, buses and interconnects) • Resource binding • Control synthesis • Clock synthesis

23. Scheduling • Assigning operations to control steps • This phase has a lot of influence on resource allocation as what can be done concurrently depends upon the resource availability • Complexity arises due to the range of available functional units (pipelined, multi-functional, multi-cycle etc.)

24. Resource Allocation • Typically manual but automating allocation algorithms are also available • FU allocation: Complexity due to the range of operators i.e. Multi-cycle, multi-function, pipelined, mixed speed operators for the same operation • Storage allocation: e.g. Registers, Memory units, Multi-port memories, Register files

25. Resource Binding • Examples of binding to be carried out are • Operation-operator binding • Variable-storage unit binding • Transfer-interconnect/bus binding • Binding has considerable influence on number of interconnects • Scheduling also influences binding

26. Control & Clock Synthesis • Generate a state machine from the control flow of the algorithm • Identify the control and status signals • Synthesize the control part • Analyze the critical path to decide on the clock period

27. Objectives in Behavioral Synthesis • Minimize delay time or maximize performance • Minimize cost or area • Meet constraints on area and/or performance

28. Recent Trends in Behavioral Synthesis • Incorporate testability conditions in synthesis • Incorporate power minimization as part of the design objective i.e. explore the design space from power considerations

29. System Level Design & Modeling M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

30. Issues in System Level Design • Specification • At different levels of design • Verification • Formal verification • Simulation • Partitioning and estimation • Synthesis

31. Characteristics of Current Systems • One (or more) processors • Heterogeneous processor set • IP cores for critical parts of the application • Mixed hardware/software implementation • Many systems are real-time reactive systems

32. System Level Design Methodology

33. Specification • Functionality • Concurrency • Time/performance constraints • Interface timings • Area and power constraints

34. Estimation • Hardware estimate • Area(cost), performance and power estimation • Software estimate • Code size, performance and power estimation • Interface estimate • Bus bandwidth and power estimation

35. Partitioning • Hardware-software partitioning • Task partitioning across multiple processors • Communication partitioning across multiple buses

36. Synthesis • Processor synthesis (ASIPs) • Application specific instruction processor • Hardware synthesis • Behavioral as well as logic • Software synthesis • Code generation and retargetable compilers • Interface synthesis

37. Formal Verification • Formal verification of functional specification by proving that the implementation is equivalent to specifications. • Theorem proving techniques • Temporal logic systems

38. Simulation Verification by simulation though expensive but is the only widely used technique. • Cosimulation e.g. C and VHDL • Test stimulus generation