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dsPIC30F4011

dsPIC30F4011. Fall 2007. DIP Switches. The upper four switches of SW1 are used to enable LEDs connected to PORTB/C, PORTA/D, PORTE and PORTF. For example, if the switch for PORTB is OFF, all PORTB LEDs will be turned off

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dsPIC30F4011

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  1. dsPIC30F4011 Fall 2007

  2. DIP Switches • The upper four switches of SW1 are used to enable LEDs connected to • PORTB/C, PORTA/D, PORTE and PORTF. For example, if the switch for PORTB is OFF, all PORTB LEDs will be turned off • Switches 5 and 6 of SW1 are used to enable SDO(Serial Data Output) and switches 7 and 8 to enable SDi (Serial Data input). • SW2 • The first two switches of SW2 are used to enable SCK, • switches 3, 4 and 5 are used for enabling CS (Chip Select) lines. • Switches 7 and 8 are used to enable LCD Backlight and GLCD Backight respectively.

  3. Jumper Settings • J16 is used as switch to connect the 4.096V voltage reference to RB0

  4. Jumper Settings • There can be used to select between different connection options

  5. Different MCU Sockets

  6. Summary

  7. Switches

  8. Power Supply

  9. Programmer

  10. ADC • Caution. What would happen if: • You are powering the board from your laptop computer, • The center pin of the potentiometers is at VCC, • It is also connected to RB0, • The switches are set to connect to ground and • Somebody presses the RB0 switch

  11. Main Features • High-Performance, Modified RISC CPU: • Modified Harvard architecture • C compiler optimized instruction set architecture with flexible addressing modes • 83 base instructions • 24-bit wide instructions, 16-bit wide data path • 48 Kbytes on-chip Flash program space (16K instruction words) • 2 Kbytes of on-chip data RAM • 1 Kbyte of nonvolatile data EEPROM • Up to 30 MIPS operation: • DC to 40 MHz external clock input • 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 1 6x) • 30 interrupt sources: • 3 external interrupt sources • 8 user-selectable priority levels for each interrupt source • 4 processor trap sources • 16 x 16-bit working register array

  12. The Modified Harvard architecture • Harvard Architecture is a computer architecture with physically separate storage and signal pathways for instructions and data • The Modified Harvard Architecture is very like the Harvard architecture but provides a pathway between the instruction memory and the CPU that allows words from the instruction memory to be treated as read-only data. This allows constant data, particularly text strings, to be accessed without first having to be copied into data memory, thus preserving more data memory for read/write variables. • In a computer with the contrasting Von Neumann Architecture (and no cache), the CPU can be either reading an instruction or reading/writing data from/to the memory. Both cannot occur at the same time since the instructions and data use the same signal pathways and memory. In a computer using the Harvard architecture, the CPU can read both an instruction and perform a data memory access at the same time, even without a cache.

  13. Harvard Architecture http://www.ee.nmt.edu/~rison/ee308_spr99/supp/990119/harvard.gif

  14. Von Neumann Architecture http://www.ccwu.edu/Thesis_Moynihan/Chapter3_files/image002.gif

  15. Pinout and Family Differences

  16. Data Memory With two address generators Program Memory Program Counter CPU Input/Output Ports Peripherals • Power-on Reset (POR), • Power-up Timer (PWRT) and • Oscillator Start-up Timer (OST) • Brown-out Reset (BOR): • A momentary dip in the power supply to the device has been detected which may result malfunction. • The Controller Area Network (CAN) module is a serial interface, useful for communicating with other CAN modules or digital signal controller devices. • The 10-bit, high-speed Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit digital number. • Input capture is useful for such modes as: • Frequency/Period/Pulse Measurements • Output Compare is useful in applications requiring operational modes, such as: • Generation of Variable Width Output Pulses • Power Factor Correction • The Inter-Integrated Circuit module provides complete hardware support for both Slave and Multi- Master modes of the 120 serial communication standard with a 16-bit interface.

  17. Data Memory With two address generators Program Memory Program Counter CPU Input/Output Ports Peripherals • The Serial Peripheral Interface (SPI) module is a synchronous serial interface. It is useful for communicating with other peripheral devices, such as EEPROMs, shift registers, display drivers and A/D converters, or other microcontrollers. • Timers 5x16 bit timers • The QEI module provides the interface to incremental encoders for obtaining mechanical position data. • PWM. This module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs. In particular, the following power and motion control applications are supported by the PWM module: • UART. UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER: • Full-Duplex, 8 or 9-bit Data Communication • PSV Program Space Visibility

  18. Device Overview • The core has a 24-bit instruction word. The Program Counter (PC) is 23 bits wide with the Least Significant bit (LSb) always clear and the Most Significant bit (MSb) is ignored during normal program execution, except for certain specialized instructions. Thus, the PC can address up to 4M instruction words of user program space. • The working register array consists of 16x16-bit registers, each of which can act as: • data, • address or • offset registers. • One working register (W15) operates as a software Stack Pointer for interrupts and calls. • Program loop constructs, free from loop count management overhead, are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

  19. Oscillator

  20. FOSC REGISTER

  21. Parallel I/O (PIO) Ports • All port pins have three registers directly associated with the operation of the port pin. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the Data Direction register bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. • Reads from the latch (LATx), read the latch. • Writes to the latch, write the latch (LATx). • Reads from the port (PORTx), read the port pins and • writes to the port pins, write the latch (LATx). • When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the Parallel Port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port.

  22. ADPCFG

  23. Timer 1 • 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle up to a match value, preloaded into the Period register, PR1, then resets to 0 and continues to count. • When the CPU goes into the Idle mode, the timer will stop incrementing unless the TSIDL (T1CON<13>) bit = 0. If TSIDL = 1, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode. • 16-bit Synchronous Counter Mode: In the 16-bit Synchronous Counter mode, the timer increments on the rising edge of the applied external clock signal, which is synchronized with the internal phase clocks. The timer counts up to a match value preloaded in PR1, then resets to 0 and continues. • When the CPU goes into the Idle mode, the timer will stop incrementing unless the respective TSIDL bit o. If TSIDL 1, the timer module logic will resume the incrementing sequence upon termination of the CPU Idle mode.

  24. Timer 1 • 16-bit Asynchronous Counter Mode: In the 16-bit Asynchronous Counter mode, the timer increments on every rising edge of the applied external clock signal. The timer counts up to a match value preloaded in PR1, then resets to 0 and continues. • When the timer is configured for the Asynchronous mode of operation, and the CPU goes into the Idle mode, the timer will stop incrementing if TSIDL = 1. • The 16-bit timer has the ability to generate an interrupt on period match. • 9.5 Real-Time Clock • Timer1, when operating in Real-Time Clock (RTC) mode, provides time-of-day and event time-stamping capabilities. • Gated Time Accumulation Mode • The Gated Time Accumulation mode allows the internal timer register to increment based upon the duration of the high time applied to the TxCK pin. In the Gated Time Accumulation mode, the timer clock source is derived from the internal system clock. When the TxCK pin state is high, the timer register will count up until a period match has occurred, or the TxCK pin state is changed to a low state.

  25. T1CON=0b1010000001101000;

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