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Lecture 5

Lecture 5 . Static CMOS Gates Jack Ou , Ph.D. 2-Input NOR Gate. F can only be pulled up if A=B=0 V F can be pulled down by either A=1 or B=1. (Or Both). 2-Input NAND Gate. F can only be pulled down if both A=B=1. F will be pulled up if either A or B is 0 V. NAND Gates. NOR Gates.

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Lecture 5

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  1. Lecture 5 Static CMOS Gates Jack Ou, Ph.D.

  2. 2-Input NOR Gate F can only be pulled up if A=B=0 V F can be pulled down by either A=1 or B=1. (Or Both)

  3. 2-Input NAND Gate F can only be pulled down if both A=B=1. F will be pulled up if either A or B is 0 V.

  4. NAND Gates

  5. NOR Gates

  6. 2-Input AND Gate NAND

  7. 2-Input OR Gate NOR

  8. Alternative Implementation for High Fanin Gates

  9. Steps for Generating Non-Trivial Static CMOS Logic Circuits 1. Implement the pull-down (NMOS)circuit using • Useful technique: DeMorgan’s Theorem • Synthesize the dual of the pull-down circuits using PMOS

  10. DeMorgan’s Theorem • The complement of a function can be obtained by • Replacing each variable with its complement • Exchange the AND and OR functions • Example • +

  11. Dual • The dual of any logic function can be obtained by exchanging the AND and OR operations. • ab ↔a+b • (a+b)c ↔ab+c

  12. A fictional AND Circuit The current flows only when both A and B are closed.

  13. Fictional OR Circuit The current flows when either A or B is closed.

  14. Implementation • Use transistors in series to implement a logical AND function • Use transistors in parallel to implement a logical OR function

  15. OAI Circuit ()

  16. XOR/XNOR

  17. Mux

  18. Determine a Boolean Expression a Schematic • Determine implemented by a NMOS pull-down network. • Complement to obtain F.

  19. 2-Input XOR XNOR (A0+A1)

  20. CMOS Gate Sizing

  21. Device Sizing • Obtain the same delay as the inverter for the rise/fall cases. • ReffN=12.5 Kohm/SQ, ReffP=30 Kohm/SQ • Reff=Reff(L/W) • ReffP/ReffN=2.4 • To achieve the same delay, (assume LP=LN, WP=2.4WN, WP/WN is approximately 2.

  22. Size Devices for the Worst Case • Series transistors: Increase W to reduce Reff. • Parallel transistors: assume the worst case, i.e. only one of the parallel transistor is ON.

  23. Transistor Sizing Without Velocity Saturation Figure 5.2 Assumption: Equal rise delay and fall delay Consideration: Effective Resistance

  24. Inverter

  25. Inverter tPHL tPHL=64.045 pS

  26. NAND2 Test Circuit

  27. NAND2 tPHL tPHL=66.01 pS

  28. Effective Width • Transistors in Series • W1||W2||W3 • Transistors in Parallel • W+W2+W3

  29. Trade-Off Increase W to reduce the effective Resistance for the pull down network. The area is increased.

  30. FO4 Fanout ratio: total capacitance driven by a gate dividing by its input capacitance

  31. VTC of Gates

  32. Adjust VS • Knob: • χ as defined in EQ. 4.15 • Increase WNLP/LNWP to decreased VS. • Decrease WNLP/LNWP to increased VS.

  33. Switching Voltage of a NAND Gate Both inputs tied together: effective WN=W, WP=4W, VS shifts to the right. Both input A=high, sweep VB: effective WN=2W, WP=2W, VS shifts to the left.

  34. Switching Voltage of a NOR Gate Both inputs tied together: effective WN=2W, WP=2W, VS shifts to the left. Both input A=ground, sweep VB: effective WN=W, WP=4W, VS shifts to the right.

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