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The Cache-Coherence Problem

The Cache-Coherence Problem. Chapter 7. Cache. Cache. Cache. Example 1: The Cache-Coherence Problem. sum = 0; begin parallel for (i=0; i<2; i++) { lock(id, myLock); sum = sum + a[i]; unlock(id, myLock); end parallel print sum; Suppose a[0] = 3 and a[1] = 7. P 1. P 2.

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The Cache-Coherence Problem

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  1. The Cache-Coherence Problem Chapter 7

  2. Cache Cache Cache Example 1: The Cache-Coherence Problem sum = 0; begin parallel for (i=0; i<2; i++) { lock(id, myLock); sum = sum + a[i]; unlock(id, myLock); end parallel print sum; Suppose a[0] = 3 and a[1] = 7 P1 P2 Pn . . . • Will it print sum = 10?

  3. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 0 Main memory Cache-Coherence Problem Illustration P1 Start state. All caches empty and main memory has Sum = 0. P2 P3

  4. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 0 Main memory Cache-Coherence Problem Illustration P1 P1 reads Sum from memory. P2 P3 Sum=0 V

  5. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 0 Main memory Cache-Coherence Problem Illustration P1 P2 reads. Let’s assume this comes from memory too. P2 P3 Sum=0 V Sum=0 V

  6. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 0 Main memory Cache-Coherence Problem Illustration P1 P1 writes. This write goes to the cache. P2 P3 Sum=0 V Sum=3 D Sum=0 V

  7. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 0 Main memory Cache-Coherence Problem Illustration P1 P2 writes. P2 P3 Sum=0 V Sum=3 D Sum=7 D

  8. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 0 Main memory Cache-Coherence Problem Illustration P1 P1 reads. P2 P3 Sum=3 D Sum=7 D

  9. Cache-Coherence Problem • Do P1 and P2 see the same sum? • Does it matter if we use a WT cache? • What if we do not have caches, or sum is uncacheable. Will it work?

  10. Cache Cache Cache Trace P1 Read Sum Bus Controller P2 Read Sum P1 Write Sum = 3 P2 Write Sum = 7 P1 Read Sum Sum = 7 Main memory Write-Through Cache Does Not Work P1 P1 reads. P2 P3 Sum=3 D Sum=7 D

  11. Cache Cache Cache Coherence with Write-Through Caches sum = 0; begin parallel for (i=0; i<2; i++) { lock(id, myLock); sum = sum + a[i]; unlock(id, myLock); end parallel Print sum; Suppose a[0] = 3 and a[1] = 7 P1 P2 Pn . . . = Snooper • Bus-based SMP implementation choice in the mid-’80s • What happens when we snoop a write? invalidating/update the block • No new states or bus transactions in this case • Write-update protocol: write is immediately propagated • Write-invalidation protocol: causes miss on later access, and memory up-to-date via write-through

  12. Bus-Based Coherent Multiprocessors Chapter 8

  13. PrRd/ – PrWr/ – PrWr/BusRdX PrRd/BusRd MSI: Processor-Initiated Transactions PrRd/ / – - PrWr/BusRdX M S Why does a PrWr in state S induce a BusRdX? I

  14. BusRd/- BusRd/Flush BusRdX/Flush BusRdX/ – BusRd/ – BusRdX/ – MSI: Bus-Initiated Transactions Thus, valid data must be supplied by memory M S I

  15. Cache Cache Cache Trace P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 1 P2 Read A Main memory MSI Visualization – Start State P1 Start state. All caches empty and main memory has A = 1. P2 P3

  16. Cache Cache Cache Trace P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 Mem P1 PrRd A BusRd A returns data P3 Read A A = 1 P2 Read A Main memory Processor P1 Reads A P1 Processor P1 attempts to read A from its cache. P2 P3

  17. Cache Cache Cache Trace P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 Mem P1 PrRd A BusRd A returns data P3 Read A A = 1 P2 Read A Main memory Processor P1 Reads A P1 Processor P1 issues a BusRd. P2 P3

  18. Cache Cache Cache Trace A = 1 S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 Mem P1 PrRd A BusRd A returns data P3 Read A A = 1 P2 Read A Main memory Processor P1 Reads A P1 Main memory returns data to processor P1 which updates its cache. P2 P3

  19. Cache Cache Cache Trace A = 1 S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 1 P2 Read A Main memory Processor P1 Reads A P1 Read operation completes. P2 P3

  20. Cache Cache Cache Trace A = 2 S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 PrWr A P3 Read A A = 1 P1 BusRdX P2 Read A Main memory Processor P1 Writes A = 2 P1 Processor P1 writes to its cache. P2 P3

  21. Cache Cache Cache Trace A = 2 M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 PrWr A P3 Read A A = 1 P1 BusRdX P2 Read A Main memory Processor P1 Writes A = 2 P1 Processor P1 issues a BusRd request. P2 P3

  22. Cache Cache Cache Trace A = 2 M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 1 P2 Read A Main memory Processor P1 Writes A = 2 P1 Write operation completes. P2 P3

  23. Cache Cache Cache Trace A = 2 M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 P3 snoops BusRd PrRd A P3 Read A A = 1 P3 P1 BusRd A Flush P2 Read A Main memory Processor P3 Reads A P1 Processor P3 attempts to read A from its cache. P2 P3

  24. Cache Cache Cache Trace A = 2 M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 P3 snoops BusRd PrRd A P3 Read A A = 1 P3 P1 BusRd A Flush P2 Read A Main memory Processor P3 Reads A P1 Processor P3 issues a BusRd. P2 P3

  25. Cache Cache Cache Trace A = 2 S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 P3 snoops BusRd PrRd A P3 Read A A = 1 P3 P1 BusRd A Flush P2 Read A Main memory Processor P3 Reads A P1 Processor P1 snoops the BusRd from processor P3. P2 P3

  26. Cache Cache Cache Trace A = 2 A = 2 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P1 P3 PrRd A snoops BusRd P3 Read A A = 2 P3 P1 BusRd A Flush P2 Read A Main memory Processor P3 Reads A P1 Processor P1 flushes, sending updated data to P3 and main memory. P2 P3

  27. Cache Cache Cache Trace A = 2 A = 2 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P3 Reads A P1 Read operation completes. P2 P3

  28. Cache Cache Cache Trace A = 2 A = 2 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P3 Writes A = 3 P1 Processor P3 writes to its cache. P2 P3 P3 PrWr A P3 BusRdX P1 snoops BusRdX

  29. Cache Cache Cache Trace A = 2 A = 2 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P3 Writes A = 3 P1 Processor P3 issues a BusRd request. P2 P3 P3 PrWr A P3 BusRdX P1 snoops BusRdX

  30. Cache Cache Cache Trace A = 2 A = 3 I M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P3 Writes A = 3 P1 Processor P1 snoops the BusRd and invalidates its cache. P2 P3 P3 PrWr A P3 BusRdX P1 snoops BusRdX

  31. Cache Cache Cache Trace A = 3 A = 2 I M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P3 Writes A = 3 P1 Write operation completes. P2 P3

  32. Cache Cache Cache Trace A = 2 A = 3 I M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P1 Reads A P1 Processor P1 reads from its cache. P2 P3 P1 PrRd A P1 BusRd A P3 snoops BusRd P3 Flush

  33. Cache Cache Cache Trace A = 2 A = 3 I M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P1 Reads A P1 Processor P1 issues a BusRd request. P2 P3 P1 PrRd A P1 BusRd A P3 snoops BusRd P3 Flush

  34. Cache Cache Cache Trace A = 2 A = 3 I M P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 2 P2 Read A Main memory Processor P1 Reads A P1 Processor P3 snoops the BusRd. P2 P3 P1 PrRd A P1 BusRd A P3 snoops BusRd P3 Flush

  35. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P1 Reads A P1 Processor P3 flushes, updating processor P1, main memory and its own cache state. P2 P3 P1 PrRd A P1 BusRd A P3 snoops BusRd P3 Flush

  36. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P1 Reads A P1 Read operation completes. P2 P3

  37. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P3 Reads A P1 Processor P3 reads from its cache. P2 P3 P3 PrRd A P3 returns data

  38. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P3 Reads A P1 Processor P3 returns valid data from its cache. P2 P3 P3 PrRd A P3 returns data

  39. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P3 Reads A P1 Read operation completes. P2 P3

  40. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P2 Reads A P1 Processor P2 reads from its cache. P2 P3 P2 PrRd A P2 BusRd A MemCntr observes BusRd Mem returns data

  41. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P2 Reads A P1 Processor P2 issues a BusRd request. P2 P3 P2 PrRd A P2 BusRd A MemCntr observes BusRd Mem returns data

  42. Cache Cache Cache Trace A = 3 A = 3 S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P2 Reads A P1 Main memory controller observes the BusRd. P2 P3 P2 PrRd A P2 BusRd A MemCntr observes BusRd Mem returns data

  43. Cache Cache Cache Trace A = 3 A = 3 A = 3 S S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P2 Reads A P1 Main memory returns valid data. P2 P3 P2 PrRd A P2 BusRd A MemCntr observes BusRd Mem returns data

  44. Cache Cache Cache Trace A = 3 A = 3 A = 3 S S S P1 Read A Bus Controller P1 Write A = 2 P3 Read A Snooper Snooper Snooper P3 Write A = 3 P1 Read A P3 Read A A = 3 P2 Read A Main memory Processor P2 Reads A P1 Operation completes. P2 P3

  45. Example: Rd/Wr to a single line *or, BusUpgr (data from own cache)

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