Flexible Arithmetic Components for Area-Efficient Fault Tolerance

1. 2003 MAPLD International Conference September 10, 2003 Flexible Arithmetic Components forArea-Efficient Fault Tolerance Vinu Vijay Kumar and John Lach Department of Electrical and Computer Engineering University of Virginia {vinuv,jlach}@virginia.edu Vijiay Kumar

2. Agenda • Motivation • Related work • Flexible components and small-scale reconfigurability • Rescheduling • Results • Conclusions Vijiay Kumar

3. Motivation • System reliability has become an important design metric for many applications • Redundancy-based fault tolerance for increased reliability • Hardware systems are growing in complexity • As complexity grows, so does the area cost of redundancy-based fault tolerance Vijiay Kumar

4. Fault Tolerance forArithmetic Datapaths • Arithmetic components • Large (compared to control circuitry) • Highly optimized and regular Min. area: 1 add, 1 mult Min. latency: 3 control steps Min. area for min. latency: 2 add, 2 mult What if a component fails? Vijiay Kumar

5. Redundancy Level • System-level redundancy • Copy entire circuit for redundancy • Coarse-grained recovery  low reliability • Component-level redundancy • Add only one type of each component for redundancy • Recoverability from any single faulty component without additional latency • Transformations and rescheduling possible for further recovery with additional latency • Subcomponent-level redundancy • Inefficient for arithmetic components Vijiay Kumar

6. Area and Reliability Comparison Adder: 75 gates Multiplier: 234 gates Comparator: 52 gates Probfailure(fault point)=0.0001 Fault points per gate: 5 Vijiay Kumar

7. Trading Off Latencyfor Extra Reliability Original DFG DFG after single component failure Guerra, J., et al., “Heterogeneous BISR reconfigurable ASIC’s synthesis,” IEEE Transactions on VLSI Systems, vol. 6, no. 1, 158-67, March 1998 Vijiay Kumar

8. Flexible Redundancy • Single flexible redundant unit can provide redundancy for multiple components • Maintain reliability with reduced area overhead by eliminating uncertainty • It does not matter which component fails • General-purpose reconfigurable fabric can provide hardware flexibility • But area, delay, and power penalties too great for many arithmetic circuits Vijiay Kumar

9. SSR: Small-Scale Reconfigurability • Primarily fixed logic • Reconfigurable logic and interconnect finely integrated with fixed logic • Finer integration than hybrid FPGAs • Only enough hardware flexibility for specific application • Reduces penalties associated with general-purpose reconfigurable fabric Vijiay Kumar

10. Flexible Arithmetic Components • Area savings if Area(flex)<Area(comp) • Operations with common subfunctions ideal • Fixed-point addition, subtraction, multiplication, bit-wise comparison • Limited Flexible Unit (LFU): adder and multiplier • Full Flexible Unit (FFU): adder, multiplier and comparator Vijiay Kumar

11. ASIC vs. SSR vs. FPGA • Area - Fixed logic components: small areas, no flexibility Comparator(52 gates), Adder(75 gates), Multiplier(234 gates) • Flexible components: moderate area, desired flexibility LFU(250 gates), FFU(276 gates) • FPGA implementation: large area, unlimited (and unused) flexibility Multiplier implemented on an FPGA(~6560 gates) • Delay - LFU(27%), FFU(36%) slower than fixed multiplier Vijiay Kumar

12. v1  v1 v3   v2 v3 v4 v2 v4 -   -  v5 v6 v5 - + v6 - + Scheduling with Flexible Components Fixed component DFG Flexible component DFG Only fixed components: 2 adders, 2 multipliers; Area = 618 gates Both fixed and flexible components: 1 adder, 1 multiplier, 1 LFU; Area = 559 gates 0 adders, 0 multipliers, 2 LFUs; Area = 500 gates Vijiay Kumar

13. v1 v1 v1 + + + v2 v3 v2 v2 v3      v4 v5 v6 v4 v3 v4 v5 + + + +  + + v7 v7 v5 v6 v7 v6 + + + + + + (a) (b) (c) Scheduling Algorithm • Scheduling based on modification of force-directed list scheduling • Minimize overall operation concurrency, not individual operations • Allocation of components on hybrid schedule Scheduling example: (a) Original DFG (b) Conventional force directed list schedule (c) Hybrid force directed list schedule Vijiay Kumar

14. Reliability and Area:Base Design Vijiay Kumar

15. Reliability and Area:With Redundancy System with 1 redundant component per type System with 2 redundant components per type Vijiay Kumar

16. Reliability with Rescheduling: Issues • Handling worst case scenarios: (Lessons learned) • Add extra redundant ‘small’ fixed components • Ensure redundancy for every operation CASE 1: 0 adders, 0 multipliers, 2 LFUs Area = 500 gates, Latency = 6 c-steps CASE 2: 1 adder, 1 multiplier, 1 LFU Area = 559 gates, Latency = 4 c-steps Vijiay Kumar

17. Reliability and Area:With Redundancy and Rescheduling Vijiay Kumar

18. Methodology - Summary • Derive an optimum implementation consisting of both fixed and flexible components • Add redundant flexible components to tolerate loss of components in the system, without increasing the number of c-steps • Add appropriate redundant fixed components to improve latency in recovery from worst case scenario • Add necessary control and interconnect for recoverability and rescheduling Vijiay Kumar

19. Conclusions • Conventional redundancy-based fault tolerance is area inefficient • Flexible components for area efficiency • Small scale reconfigurability to optimize flexible component design • Reliability via redundancy and/or rescheduling • Considerable area savings with nearly equal reliability Vijiay Kumar