AID–EMC: Low Emission Digital Circuit Design

1. AID–EMC: Low Emission Digital Circuit Design Design-In for EMC on digital circuit October 27th, 2005 Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS

2. Outline Introduction 2. Logic family selection 3. Clock strategy selection (not discuss today due to lack of time) 1. clock skew 2. SSCG 3. Delay cell array approach 4. Low noise power supply – EMI reducer 1. continuous time 2. stability analysis 3. future work

3. Part I: Introduction • Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for high speed digital circuit, • Most of them are due to power and ground fluctuation. • Although the detailed calculation of EMI noise is rather difficult , we can use the di/dt as the index, since the current loop contributes the EMI.

4. Part 2: Logic Family Selection PNMOS RSBCMOS SCMOS MCML FSCL CSL

5. Comparison of di/dt ,power and area (Static + Dynamic) Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Ring Oscillator of 21-stages But there is static power !! Current Steering Logic

6. Detailed comparison of CSL and SCMOS CSL One-bit Adder IT is a static power problem, Switching off when standby ? Note: The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I.

7. Detailed comparison of CSL and SCMOS SCMOS SCMOS CSL CSL

8. Problem with CSL • Mismatch sensitive, annoying for standard cells • rather slow/power hungry • Not full swing Matching required! M1 > M3

9. Can we do it better ? CBL C-CBL: • sizing for optimal current balance is really difficult ,process dependent [Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]

10. Solution- Enhanced current steering logic • Still current source basing • Increase in logic level, hence increase the robustness • Reduced output capacitance, hence the speed is increased Minimum size Fig.3 E-CSL inverter

11. Comparison of CSL, C-CBL, ECSL and SCMOS Ring Oscillator of 21-stages Fig.4 power vs. frequency Fig.5 di/dt vs. frequency

12. di/dt performance vs. process variation MAX di/dt change MIN di/dt change Ring Oscillator of 21-stages Fig.6 di/dt vs. process corner

13. Conclusion of Low noise Logic Families • CSL,E-CSL show a smaller area per logic function for complex digital gates and systems compared to SCMOS logic technique. • Current source ensures the major di/dt reduction, • Process variation sensitivity also becomes better due to the dominance of current source, • E-CSL gives comparable di/dt performance with CSL, • E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance. • Static power consumption remains the challenge for wide application of the CSL,E-CSL technique in very large digital systems. Can be solved by using power down strategies, which is highly application dependent Winner is E-CSL

14. Part 4: Low Noise Power Supply design However 2 problems still remain: • Static power consumption • New logic family standard cell library must be designed and characterised. (large NRE cost, risk) ?? Is there any global approach ??

15. Principles of Low Noise Power supply Can be done with switched or continuous mode. Both are studied, 2. Continuous mode potentially has better di/dt suppression. Current source ensures the major di/dt reduction 2. Do not give more current than the circuit needs, i.e. minimize the static current 3. Slow varying is key to EMC success Fig.9 Diagram of Low noise power supply

16. Continuous mode Power Delivery Determine the switching speed, Hence determine the di/dt Energy reservoir when slow Switching Fig.13 Continuous time power delivery system

17. Functionality Simulation 9v Idd VDD_input VDD_input 2nd order under damped behaviour , still under study continuous time OTA feedback loop stable Vcontrol Vcontrol di/dt Fig.14 Functionality simulation of continuous time power delivery system

18. Comparison with standard CMOS 12v supply current 162 times= 44dB w/o CT, 3.3V only 12v supply current di/dt p-p = 1.0x107A/s di/dt w/o CT, di/dt p-p =1.51x1011A/s Fig.15 di/dt and FFT comparison with standard CMOS

19. Stability analysis - Small signal analysis Approximation: dominant pole p3 second-dominant pole high frequency poles p4 mirror factor p1 >3 for > 72° phase margin(2nd order system) p2

20. Stability analysis- Calculation vs. Simulation (dB) MapleSpectre --------------------------------------------------------------- DC gain(dB): 97.72 97.25 --------------------------------------------------------------- Phase Margin(degree): 62.5 49 --------------------------------------------------------------- Gain Crossover(Hz): 325K 275K ---------------------------------------------------------------- P2/GBW: 1.275 1.264 ---------------------------------------------------------------- (deg)

21. Trade-off in Ctank and Caux Ctank=100pF Caux=100pF P2/GBW P2/GBW 3 3

22. Current pulse step response An input current step of 1 mA and 100-ps rise time was used for the calculation and simulation Can be improved if more stable ~104 reduction !!

23. Coupling problem ! Cgs1,2≈ Cgd1 ∆ Vbias ∆ VDD_input

24. Future work • Improve circuit structure to reduce coupling between output node and gate of the current source transistor • Figure out supply current behaviour of a typical AMIS digital block • Add a real voltage regulator into consideration

25. Questions Thank you for your attention