Computer Systems Organization & Architecture Chapter 1 Part 8 Counters

1. Computer Systems Organization & Architecture Chapter 1 Part 8 Counters

2. Counter: a sequential circuit that goes through a set of given states on successive clock cycles A state is the binary value represented by the outputs Usually the states are sequential: 0-7, 0-15, etc. Counters

3. Counter uses Timing applications Multiplexing counting Counters

4. Cannot create a counter in the hardware simulator with T (or JK) flip flops. no JK flip flop built-in cannot create a JK flip flop as described earlier because feedback loops are not allowed in the hardware simulator. Counters

5. T flip-flop: tie J and K high on a J-K flip-flop After two clock cycles, the output completes one cycle Use the output of this flip-flop as the clock input to a second T flip-flop Output of the second flip-flop cycles at half the rate of the first flip-flop Each additional flip-flop added cycles in half the rate of its preceding flip-flop Asynchronous Ripple Counters

6. Timing diagram for 2-bit Ripple Counter Asynchronous Ripple Counters clock Qa Qb 00 01 10 11 00 01 10

7. Output: Transitions occur on the falling edge of the clock Use the output of the first flip-flop (Qa) as the 1’s digit the output of the second flip-flop as the 2’s digit Result is binary counter sequencing from 0 through 3 Then repeats Asynchronous Ripple Counters

8. Circuit implementing simple 0-3 ripple counter Qa Qa J J Ck Ck ~Qa ~Qa K K Asynchronous Ripple Counters 2s 1s Clock in J and K inputs are tied high

9. Circuit implementing simple 0-7 ripple counter Qa Qa Qa J J J Ck Ck Ck ~Qa ~Qa ~Qa K K K Asynchronous Ripple Counters 2s 1s 3s Clock in J and K inputs are tied high

10. Timing The timing diagram shows state transitions occurring exactly on falling edge of clock Not true. Change in wave takes time Flip-flops take time to change state Timing in the 2-bit counter using the 7476 flip-flop 1s digit (Qa) changes 40ns after the falling edge of clock 2s digit (Qb) changes 40ns after the falling edge of Qa or 80ns after falling edge of clock Asynchronous Ripple Counters

11. Timing Each additional bit requires 40ns more Clock signal ripples through the counter Each flip-flop does not change state on a common clock signal, thus asynchronous Asynchronous Ripple Counters

12. Timing Maximum speed of ripple counter depends on the switching delay of the flip-flops The number of flip-flops Asynchronous Ripple Counters

13. Timing Longest delay in 4-bit counter: all 4 flip-flops must change state From state 7 (0111) to state 8 (1000) From state 15 (1111) to state 0 (0000) Maximum switching delay: 4 X 40 ns = 160 ns Maximum counting rate: 1/160 ns = 2.25 MHz Asynchronous Ripple Counters

14. Timing delay Asynchronous Ripple Counters 40 ns Clock Qa Qb Qc 160 ns Qd 1111 1110 1100 1000 0000

15. Timing Problem: each state must exist for some short time before the next clock pulse Allows other circuit parts to use the value Max counting rate would actually be lower than 2.25 MHz since states 0 and 8 only exist a short time. Asynchronous Ripple Counters

16. Timing Problem Counter might be used as a memory location But as 4-bit ripple counter goes from state 15 to state 0 it passes through states: 14 (1110), 12 (1100), and 8 (1000). Stays in each state 40 ns. Called glitches or decoding spikes Any time more than one flip-flop must change state a glitch will arise. Asynchronous Ripple Counters

17. Timing Problem Example: counter used to drive a LED display When go from 15 to 0, will display the numbers 14, 12, and 8 for 40 ns each. Human eye cannot see this Other digital devices can! Must allow time for circuit to “settle” before try to read its value! Asynchronous Ripple Counters

18. Can use ripple counters to divide rate of a clock signal Example: Circuit has clock running at 10 MHz Needs another clock running at 5 MHz Get the latter by dividing the former in half Generating Clock Signals

19. Output of T flip-flop cycles at half the rate of the input clock. See earlier. If 10 MHz clock signals the circuit, output cycles at one half that rate, or 5 MHz. So a 1-bit ripple counter performs a divide-by-2 Add a second T flip-flop Cycles at half the rate of its input clock (the output of first flip-flop) Or at one fourth rate of the original clock Generating Clock Signals

20. So far, number of states in counter is power of 2 Goal: have counter reset after arbitrary number of states Method: add circuitry to force a reset earlier. Example: counter goes 0 to 7 Add circuit to force it to go to 0 after state 5 Now have a 0 to 5 counter Modifying the Count Sequence

21. Commercial J-K flip-flops have clear input. This resets output to 0 0-5 counter: must reset flip-flops to 0 when counter tries to change state to 5 Add circuit to activate the clear inputs of all flip-flops when this happens. Happens when bits 0 and 2 are 1. The only other situation when these bits are 1 is state 111, but this will never be reached. See next slide. Modifying the Count Sequence

22. Qa Qa Qa J J J Ck Ck Ck ~Qa ~Qa ~Qa K K K Modifying the Count Sequence Output Clock in clr clr clr

23. Note that clear is active low NAND gate turns on when the first and last bits of output are 1 (five is 101). Timing diagram: next slide 40 ns after falling clock edge Qa goes to 1 State is now 101 Both inputs to the NAND are 1 10 ns later (switching time for NAND) output of NAND goes low Clear operation on 7476 J-K flip-flop takes 40 ns Output cleared after 90 ns (40 ns + 10 ns + 40 ns). State 5 exists for 50 ns, but this does not effect Qc Modifying the Count Sequence

24. Switching from state 4 to 0 Modifying the Count Sequence 40 ns Clock Qa 50 ns Qb Output (Qc) 90 ns 100 101 000

25. Problem: The wave generated by the divide-by-5 counter is not symmetric. It is 0 for 4 input clock cycles (000 thru 011) It is 1 for one input clock cycle (100) See next slide. Numbers at bottom indicate current state of the counter after each transition. Switching delays not shown Generating a Symmetric Waveform

26. Problem: Generating a Symmetric Waveform 3 4 0 1 2 3 4 0 1 2

27. Problem: some applications require square waveform Wave has value 1 just as long as it has 0 Cannot do this when dividing the clock by an odd value. More symmetric waveform can be obtained by taking output from a different counter output. Generating a Symmetric Waveform

28. Example: divide by 5 counter. Generating a Symmetric Waveform Both Qcand Qbcycle once So can use Qbas output Qbis more symmetric

29. Which outputs can be used as clock output? Depends on sequence length Problem: some outputs have glitches. In switching from state 4 to 0 Qaappears to remain 0 But temporarily goes to 1 If use Qa as output there will be a 40 ns glitch. Generating a Symmetric Waveform

30. If desired sequence length is even, can generate a completely symmetric waveform. Break an even divide operation into two divide operations Make the last a divide-by-2 operation Will get a symmetric waveform. Requires no extra flip-flops Need one extra for the divide-by-2 operation But need one less to do original divide See next slide: divide-by-6 ripple counter. Generating a Symmetric Waveform

31. divide-by-6 ripple counter. Right two flip-flops form divide-by-3 counter NAND gate resets counter to 0 when switching from state 2 to 3 Leftmost flip-flop is the divide-by-2 counter. Take output from the divide-by-2 counter. Generating a Symmetric Waveform

32. Qa Qa Qa J J J Ck Ck Ck ~Qa ~Qa ~Qa K K K Generating a Symmetric Waveform Output Clock in clr clr clr

33. Multiplexing applications, pulse timing, pulse counting, frequency measurement, analog-to-digital converts. Other Applications of Counters

34. Ripple counter used to provide the select-line sequence for the multiplexor or decoder. Glitches special problem Multiplexing

35. A counter can be easily started and then stopped by two consecutive input pulses. Clock the counter at a known rate between the pulses Can determine the time between them Number of bits in the counter and the max counting rate are primary design consideration Pulse Timing

36. Pulses are used as the clock input for the counter. Count over a given period of time Can determine the average frequency of the pulses Considerations: Number of bits Max counting rates Pulse Counting

37. Converts an input voltage into a binary value representing that voltage. Example: an 8-bit A/D converter might be used to convert a voltage between 0 and 5 volts into a binary value between 0 and 255. Many ways of doing this, several with counters Analog-to-digital converter

38. One method: Outputs of a counter feed the inputs of a digital-to-analog converter. For each ouput of the counter, the D/A converter will output a different voltage. A device to compare voltages called a comparator is used to determine when the output of the D/A converter is greater than the input voltage. When it is, the counter is stopped The value in the counter represents the binary value of the input voltage. Analog-to-digital converter

39. Page 38, Figure 1.31

40. Page 40, Figure 1.32

41. Page 41, Figure 1.33

42. Page 42, Figure 1.34

43. Page 44, Figure 1.35

44. Page 45, Figure 1.36

45. Page 48, Problem 1.9