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Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams

EWDTS’09. Tallinn University of Technology. Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams. Maksim Jenihhin Jaan Raik Anton Chepurov Raimund Ubar. Agenda. Overview Assertion-based verification with HLDD

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Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams

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  1. EWDTS’09 Tallinn University of Technology Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams • Maksim Jenihhin • Jaan Raik • Anton Chepurov • Raimund Ubar

  2. Agenda • Overview • Assertion-based verification with HLDD • Verification coverage analysis with HLDD • Conclusions • Overview • Assertion-based verification with HLDD • Verification coverage analysis with HLDD • Conclusions Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  3. The scope • Functional verification of digital hardware • on model • Objectives • speed • accuracy • Not considered • Prototype validation • Manufacturing testing Specification Verification Design phase Assertions Manufacturing Testing Product Maintenance Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  4. APRICOT verification framework Stimuli (Testbench) Test vectors in plain text HLDD-based Simulation Variety of HLDD representation types RTL to Beh. Coverage Analysis Assertion Checking VHDL to HLDDInterface HLDD Model Design (VHDL) Converters via Intermediate Formats of APRICOT Partners Debugger Coverage mapping THLDD Model PSL to THLDDInterface Application-optimized THLDD PSL FL Subset Assertions (PSL) ATPG and Formal Property Checking (DECIDER engine) Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  5. High-Level Decision Diagrams (HLDDs) • Proposed by Prof. Raimund Ubar (TUT) • Generalization of BDDs • Design is a system of HLDDs • RTL to behavioral abstraction levels • non-terminal nodes • conditional statements, control signals • edges • scalar variable values • terminal nodes • assignment statements, operations • Previous works: HLDDs are efficient for simulation and diagnosis • faster in times compared to commercial simulators • easy identification of cause-effect relationships m2 m2 m2 m2 m2 m0 m0 m0 m0 m0 m1 m1 m1 m1 m1 y y y y y 2 2 2 2 2 x2 x2 x2 x2 x2 0 0 0 0 0 x3 x3 x3 x3 x3 x4 x4 x4 x4 x4 e1 e1 e1 e1 e1 e4 e4 e4 e4 e4 {x1, x2, x3, x4} = {4, 2, - ,-} y = 4 e5 e5 e5 e5 e5 m3 m3 m3 m3 m3 0,1,3 0,1,3 0,1,3 0,1,3 0,1,3 1-3 1-3 1-3 1-3 1-3 x1 x1 x1 x1 x1 e2 e2 e2 e2 e2 m4 m4 m4 m4 m4 4-7 4-7 4-7 4-7 4-7 x2 x2 x2 x2 x2 e3 e3 e3 e3 e3 Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  6. Agenda • Overview • Assertion-based verification with HLDD • Verification coverage analysis with HLDD • Conclusions Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  7. Assertion based verification • assertion = asserted property • a part of the design’s behavior • Simulation-based verification: • Speed-up • Quality improvement • IEEE1850-2005 PSL • Property Specification Language Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  8. Temporally extended HLDDs • Acyclic graphs with hierarchy support • Capable to represent complex temporal relations • Exactly 3 terminal nodes vs. arbitrary number for HLDD • Support for a wide set of PSL Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  9. PSL to THLDD conversion P P P P P P [ tmin = 0; tmax = tend ] tmin = 0; tmax = tend tmin = 0; tmax = tend tmin = 0; tmax = tend tmin = 0; tmax = tend tmin = 0; tmax = tend 0 T a=b readyt={1,...,3} ready P1 P3 P4 P7 P4 P5 P5 P5 P6 t={1,...,3} P6 t={1,...,3} P3 P2 F T F 1 FAIL FAIL FAIL FAIL FAIL FAIL PASS PASS PASS PASS PASS PASS CHK. CHK. CHK. CHK. CHK. CHK. PSL property: P: assert always((not ready) and (a=b) ->next_e[1 to 3]( ready)); PSL property: ________________P1__________________ P: assert always((not ready) and (a=b) ->next_e[1 to 3]( ready)); PSL property: _______P2 ______ _______P3 _______ P: assert always((not ready) and (a=b) ->next_e[1 to 3]( ready)); PSL property: _P7 _ _P5 _ _P6 _ P: assert always((not ready)and(a=b) ->next_e[1 to 3]( ready)); PSL property: ___P4 __ _P5 _ __P6 _ P: assert always((not ready)and(a=b) ->next_e[1 to 3](ready)); PSL property: _P7 _ _P5 _ _P6 _ P: assert always((not ready)and(a=b) ->next_e[1 to 3]( ready)); PSL property: ___P4 __ _P5 _ ________P3 ______ P: assert always((not ready)and(a=b) ->next_e[1 to 3]( ready)); PSL property: P: assert always((not ready) and (a=b) ->next_e[1 to 3]( ready)); Pz Pz Pw Pe Pe Pb Pf Pc Pd Pb Pa Pc Pd Pw Pf Pa PSL Parser Hierarchical Recursive Constructor Pa Pc Pw Pd Pz PPG Library: PPG Library: PSL operators: always (P1); (P2) -> (P3); (P4) and (P5); next_e[1 to 3](P6); not (P7); Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  10. Assertion Checking with HLDDs Stimuli (Testbench) Stimuli (Testbench) Test vectors in plain text Test vectors in plain text HLDD-based Simulation HLDD-based Simulation Variety of HLDD representation types Variety of HLDD representation types RTL to Beh. RTL to Beh. Coverage Analysis Coverage Analysis Assertion Checking Assertion Checking VHDL to HLDDInterface VHDL to HLDDInterface HLDD Model HLDD Model Design (VHDL) Design (VHDL) Converters via Intermediate Formats of APRICOT Partners Converters via Intermediate Formats of APRICOT Partners Debugger Debugger Coverage mapping Coverage mapping THLDD Model THLDD Model PSL to THLDDInterface PSL to THLDDInterface Application-optimized THLDD Application-optimized THLDD PSL FL Subset PSL FL Subset Assertions (PSL) Assertions (PSL) ATPG and Formal Property Checking (DECIDER engine) ATPG and Formal Property Checking (DECIDER engine) Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  11. Experimental results (assertion checking) • The processing time is shown in seconds • The length of the test sets is 1M clock cycles Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  12. Agenda • Overview • Assertion-based verification with HLDD • Verification coverage analysis with HLDD • Conclusions Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  13. Application of verification coverage • Simulation-based verification • The fundamental question is: • when is the design simulated (verified) enough? Design Stimuli Simulation Tool Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  14. A VHDL descript. for an example design if (cS1_C1 and cS1_C2) then V1 <= V1_T1; else V1 <= V1_T2; end if; case cS2_C is when cS2_C_W1 => V2 <= V2_T1; when cS2_C_W2 => V2 <= V2_T2; when cS2_C_W3 => V1 <= V1_T2; if(cS3_C1 and ((not cS3_C2) or cS3_C3)) then V2 <= V2_T2; else V2 <= V2_T3; end if; end case; 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 2 3 4 5 6 7 if (cS1_C1 and cS1_C2) then V1 <= V1_T1; else V1 <= V1_T2; end if; casecS2_C is when cS2_C_W1 => V2 <= V2_T1; when cS2_C_W2 => V2 <= V2_T2; when cS2_C_W3 => V1 <= V1_T2; if(cS3_C1 and ((not cS3_C2) or cS3_C3)) then V2 <= V2_T2; else V2 <= V2_T3; end if; end case; • Statements • Conditional • Assignment • Branches • Conditions Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  15. HLDD representation for the design Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  16. Coverage analysis with HLDDs Stimuli (Testbench) Stimuli (Testbench) Test vectors in plain text Test vectors in plain text HLDD-based Simulation HLDD-based Simulation Variety of HLDD representation types Variety of HLDD representation types RTL to Beh. RTL to Beh. Coverage Analysis Coverage Analysis Assertion Checking Assertion Checking VHDL to HLDDInterface VHDL to HLDDInterface HLDD Model HLDD Model Design (VHDL) Design (VHDL) Converters via Intermediate Formats of APRICOT Partners Converters via Intermediate Formats of APRICOT Partners Debugger Debugger Coverage mapping Coverage mapping THLDD Model THLDD Model PSL to THLDDInterface PSL to THLDDInterface Application-optimized THLDD Application-optimized THLDD PSL FL Subset PSL FL Subset Assertions (PSL) Assertions (PSL) ATPG and Formal Property Checking (DECIDER engine) ATPG and Formal Property Checking (DECIDER engine) Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  17. Experimental results (coverage analysis) Code Coverage, % • Code coverage analysis with APRICOT is more stringent (accurate) ITC99 : b01 b06 b09 Time overhead, seconds HLDD based VHDL based not covered (good!) HLDD based VHDL based • Code coverage analysis with APRICOT is faster ITC99: b00 b04 b09 gcd Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  18. Agenda • Overview • Assertion-based verification with HLDD • Verification coverage analysis with HLDD • Conclusions Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  19. Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  20. Conclusions • HLDD-based analysis has a better performance than HDL-based one • faster HLDD-based simulation • lower computational overheads • APRICOT relies on a homogeneous hardware verification flow • Uniform computational model (HLDD) • Potential for diagnosability(debug) Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  21. Thank You! Maksim Jenihhin: maksim@computer.org APRICOT web: http://apricot.pld.ttu.ee Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  22. EWDTS’09 Tallinn University of Technology Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams Maksim Jenihhin Jaan Raik Anton Chepurov Raimund Ubar

  23. Conclusions • The proposed approaches rely on a homogeneous hardware verification flow • single design representation model (HLDD) • HLDD-based analysis has a better performance than HDL-based one • faster HLDD-based simulation • lower computational overheads • THLDD model is capable to represent complex temporal properties and supports a wide set of PSL language • Different HLDD representation types with consideration of the target application • compactness: { minimal | reduced | full-tree } • conditional statements: { collapsed | expanded } Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  24. Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  25. Experimental results (coverage analysis) Code Coverage, % ITC99 benchmarks: b01 b06 b09 reduced HLDD minimized HLDD VHDL not covered (good!) Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  26. Experimental results (coverage analysis) Time overhead, % ITC99 benchmarks: b00 b04 b09 gcd HLDD based VHDL based • Coverage measurement time overhead Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  27. Experimental results (assertion checking) • The processing time is shown in seconds • The length of the test sets is 1M clock cycles Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  28. APRICOT verification framework (TUT) Stimuli (Testbench) Test vectors in plain text HLDD-based Simulation Variety of HLDD representation types RTL to Beh. Coverage Analysis Assertion Checking VHDL to HLDDInterface HLDD Model Design (VHDL) Converters via Intermediate Formats of APRICOT Partners Debugger Coverage mapping THLDD Model PSL to THLDDInterface Application-optimized THLDD PSL FL Subset Assertions (PSL) ATPG and Formal Property Checking (DECIDER engine) Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  29. Temporal constructs of THLDD Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  30. HLDD reduction rules • 1: Eliminate all the redundant nodes whose all edges point to an equivalent sub-graph • 2:Share all the equivalent sub-graphs ... ... ... ... ... ... x x x x 1 0 1 0 0 0 1 1 sG sG sG0 sG1 sG0 sG1 Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  31. Full-tree HLDD • contains all control flow branches Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  32. Reduced HLDD • full-tree + reduction rule 1 Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  33. Minimized HLDD • full-tree + reduction rule 1 + reduction rule 2 Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  34. Example study 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 if (cS1_C1 and cS1_C2) then V1 <= V1_T1; else V1 <= V1_T2; end if; casecS2_C is when cS2_C_W1 => V2 <= V2_T1; when cS2_C_W2 => V2 <= V2_T2; when cS2_C_W3 => V1 <= V1_T2; if(cS3_C1 and ((not cS3_C2) or cS3_C3)) then V2 <= V2_T2; else V2 <= V2_T3; end if; end case; Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  35. Example study: test vectors Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  36. Structural coverage base metrics if (cS1_C1 and cS1_C2) then V1 <= V1_T1; else V1 <= V1_T2; end if; case cS2_C is when cS2_C_W1 => V2 <= V2_T1; when cS2_C_W2 => V2 <= V2_T2; when cS2_C_W3 => V1 <= V1_T2; if(cS3_C1 and ((not cS3_C2) or cS3_C3)) then V2 <= V2_T2; else V2 <= V2_T3; end if; end case; 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 • Statements • Conditional • Assignment • Branches Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  37. Base coverage metrics mapping • Statements • Conditional • Assignment • Branches Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  38. Example study: HDL vs. HLDD coverage • HLDD coverage analysis is more accurate than the VHDL-based one • The condition coverage metric adds an “orthogonal dimension” Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  39. Example study 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 if (cS1_C1 and cS1_C2) then V1 <= V1_T1; else V1 <= V1_T2; end if; casecS2_C is when cS2_C_W1 => V2 <= V2_T1; when cS2_C_W2 => V2 <= V2_T2; when cS2_C_W3 => V1 <= V1_T2; if(cS3_C1 and ((not cS3_C2) or cS3_C3)) then V2 <= V2_T2; else V2 <= V2_T3; end if; end case; Stm. & Branch 100% Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  40. A success story of one Ph.D. forum Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

  41. Maksim Jenihhin, "Simulation-based Verification with APRICOT Framework using High-Level Decision Diagrams", EWDTS'09

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