EKT 221 : DIGITAL 2 BINARY MULTIPLIER

1. EKT 221 : DIGITAL 2BINARY MULTIPLIER

2. ASM : Binary Multiplier Example Multiplier Multiplicand Note that the partial product summation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column. Partial Products are: 101 x 1 101 x 1 101 x 0 Note also n x m digit multiply generates up to an m + n digit result (same as decimal).

3. 1 1 0 0 1 1 0 x 101 = 0 0 0 1 x 101 = 1 0 1 ASM : Binary Multiplier Example A Multiplier (Q) Multiplicand (B) 0 0 0 0 1 1 1 0 1 0 0 0 + 1 0 1 1 0 1 1 x 101 = 1 0 1 • MUL LSB with Multiplicand OR check if LSB = 1, if 1 then do addition • ADDITION (A + B) • SHIFT Right A Multiplier (Q) Multiplicand (B) 0 1 0 1 0 1 0 0 1 0 + 1 0 1 1 1 1 • MUL LSB with Multiplicand OR check if LSB = 1, if 1 then do addition • ADDITION (A+B) • SHIFT Right Multiplicand (B) A Multiplier (Q) 0 1 1 1 1 0 0 • MUL LSB with Multiplicand OR check if LSB = 1, if 0 then do not do Addition • SHIFT Right Product 0 0 1 1 1 1 0

4. ASM : Binary Multiplier Example A Multiplier (Q) Multiplicand (B) 0 0 0 0 1 1 1 0 1 • Multiplicand is loaded into Reg. B • Multiplier is loaded into Reg. Q • Reg. A is initially zero • Parallel Adder is used to add Reg. A and Reg B • C FF’s stores Cout of P.A • C is Reset to 0 upon shift right • Counter P is provided to count the cycle • If P=0 then read result in Reg. A and Reg. Q. and processing stops. • CU stays in initial state until G=1 • In the initial state, Reg. A and FF C is reset to 0. • After Shifting Right, Reg. A will send the content to P.A for next cycle. • The LSB of Q is discarded. • CU will check for signal Z and Q0. • CU will decide to add/shift or shift based on this 2 signals. • The control signal from the CU to the datapath activate the required microoperations Figure 8-6, Morris Mano, pg 371

5. Multiplier ASM Chart • Three main states are employed: • IDLE - state in which: • the outputs of the prior multiply is held until Q is loaded with the new multiplicand • input G is used as the condition for starting the multiplication, and • C, A, and P are initialized • MUL0 - state in which: • conditional addition is performed based on the value of Q0. • MUL1 - state in which: • right shift is performed to capture the partial product and position the next bit of the multiplier in Q0 • the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.

6. Multiplier ASM Chart Figure 8.7 : Morris Mano, pg 373

7. Analysis of ASM Chart • ASM = IDLE and G=0, no action occurs • Multiplication ONLY occurs when G=1. • Moving to state MUL0, C & A are cleared to 0 and P is loaded with (n-1). • In state MUL0, a decision is made based on Q0: • Q0 = 1, B add to A, result transferred to A and Carry to C • Q0 = 0, A & C unchanged. • Note : Both condition will go to next state MUL1 • A Shift Right is performed on the combined content of C, A and Q.

8. Analysis of ASM Chart….cont • The shift transfer can be simplified to: C 0, C || A || Q sr C || A || Q • || is called concatenation, meaning it is a composite register or register made up of other registers. • Counter P is decremented in state MUL1. This illustrates a very IMPORTANT timing difference between a standard flowchart and an ASM chart. • The decision on Z, which represent P=0, follows the register transfer statement that updates P in the ASM chart.

9. Hardware selection • Identifying h/w is also important: • Reg. A = Shift Reg with parallel load, with CLR enable to reset the reg. to “0”. • Reg. Q = Shift Reg • C FF’s = accept input from Cout, with CLR enable to reset the FF to “0”. • Reg. B and Q = Parallel load Reg, used to load multiplier and multiplicand at the initial stage.

10. Thank you