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Energy-Efficient CMOS Comparators for High-Performance Microprocessors

Implementing fast, energy-efficient CMOS comparators for modern datapaths, proposing dissipate-on-match designs to save energy, presenting traditional and two-stage comparator evaluations and timing diagrams.

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Energy-Efficient CMOS Comparators for High-Performance Microprocessors

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  1. ICCD 2002 A Circuit-Level Implementation ofFast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors* Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev Department of Computer Science State University of New York Binghamton, NY 13902-6000 http://www.cs.binghamton.edu/~lowpower International Conference on Computer Design (ICCD 2002), September 16th 2002 *supported in part by DARPA through the PAC-C program and NSF

  2. ICCD 2002 A Superscalar Datapath Function Units Architectural Register File Instruction Issue IQ FU1 F1 F2 D1 D2 FU2 ROB ARF FUm Fetch Decode/Dispatch LSQ EX Instruction dispatch D-cache Result/status forwarding buses

  3. ICCD 2002 Motivation • Comparators are in a pervasive use in modern datapaths. They are used in: • Issue queues • Load-Store queues • TLBs • Caches • Associatively-addressed Reorder Buffers • Dependency checking logic • CAM-based rename tables

  4. ICCD 2002 Motivation (continued) • Traditional comparators dissipate energy on mismatches • In many cases, mismatches are much more frequent than matches • To save energy, we propose two dissipate-on-match comparators: • A Two stage Domino-style design • Pass-logic single stage design • First, traditional comparator…

  5. precharge Evaluation ICCD 2002 Traditional 8-bit Pull-Down Comparator

  6. Precharge (Conditional evaluation) Propagation Discharge Evaluation ICCD 2002 Two-Stage Domino-Style Comparator

  7. Precharge Propagation Discharge Evaluation ICCD 2002 Pass Logic, Single-Stage Comparator (PLSSC)

  8. ICCD 2002 Timing Diagrams

  9. ICCD 2002 Experimental Setup (AccuPower, DATE’02) Compiled SPEC benchmarks Performance stats Microarchitectural Simulator Datapath specs Transition counts, Context information Power/energy stats Energy/Power Estimator VLSI layout data SPICE SPICE deck SPICE measures of Energy per transition

  10. ICCD 2002 Variation of Response Time with Vs

  11. ICCD 2002 Variation of Energy Dissipation with Vs

  12. ICCD 2002 Matching Statistics: the Issue Queue

  13. ICCD 2002 Energy Dissipation in Various Matching Cases

  14. ICCD 2002 Main Results • Two-stage domino-style comparator: • 65% comparator energy reduction in the issue queue • About 25% increase in response time • PLSSC: • 75% comparator energy reduction in the issue queue • Slight improvement in response time • PLSSC is the design of choice for 8-bit comparands. Domino-style design is a more scalable solution.

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