PIC Architecture Programmers Model and Instruction Set

1. PIC ArchitectureProgrammers Model and Instruction Set Lecture 21 -PIC Architecture

2. PICs-Programmer’s Model & Instruction Set • Programmer’s Model • Instruction Set Basics • Accumulator Architecture • Direct addressing • Indirect addressing • Interrupt • F/W ??? Lecture 21 -PIC Architecture

3. Registers Programmer Can See Lecture 21 -PIC Architecture

4. Accumulator Architecture • In the CPU have an accumulator • Onboard RAM is “banked” • ACCESS RAM can be viewed as a set of 7f registers • 7f = 128 8-bit registers • The Access Bank is Bank 0 • Outside addresses 0000 to 007f access to RAM are considered Banked direct addressing and use the BSR register Lecture 21 -PIC Architecture

5. Banked Addressing – Direct Addressing Mode • Each bank has ff bytes of 8-bit data • User defines how larger data is stored • Big Endian • Little Endian • Multiple byte operations are supported through carry bit Lecture 21 -PIC Architecture

6. When BSR is loaded with value • Up to ff bytes can be addressed with direct addressing • Example • Load BSR value with value 0x01 • Then can address 0x100 to 0x1ff • Transparent to programmer as assembler (or compiler) handles “banking” of variables Lecture 21 -PIC Architecture

7. Indirect Addressing • Uses a pointer to access the data • Uses the FSRx registers • Consider the example to add two 3-bit numbers Lecture 21 -PIC Architecture

8. Adding two 3-bit numbers Lecture 21 -PIC Architecture

9. Explanation • First load FSR0 with address of NUM1 • Load FSR1 with address of NUM2 • Set a variable, COUNT, to 3 (2 instructions) • Clear carry bit • Loop to do addition • Add instruction returns result to address indicated by FSR0 • Decrement loop counter and repeat till done Lecture 21 -PIC Architecture

10. Operand names of indirect registers Lecture 21 -PIC Architecture

11. Special Program addresses • Address 0x0000 • The reset vector • Address 0x0008 • High-priority interrupt vector • Address 0x0018 • Low-priority interrupt vector Lecture 21 -PIC Architecture

12. Interrupt action • Program Counter sent to stack • Low-priority interrupts disabled • If a high-priority interrupt then high-priority interrupts also disabled • Contents of key registers copied to shadow registers • Program counter set to interrupt address for level of interrupt • Instruction executed for this is a “goto” branch and a 2-byte instruction with the vector being the second byte Lecture 21 -PIC Architecture

13. Special Function Registers • Located at addresses 0xf80 to 0xfff • 2 byte registers are LSB then MSB Lecture 21 -PIC Architecture

14. Concept of instructions • A Harvard accumulator architecture • A lot of time moving data for operation • To add two variables • Load Variable A into accumulator • Add Variable B • Store result Lecture 21 -PIC Architecture

15. Instruction Set • F/W distinction • Indicates where result is to stored • movf NUM2, W • Moves the 8-bit byte in NUM2 to the W register • addwf NUM1,F • Adds and return results to NUM1 • decf NUM1,W • Decrement and leave accumulated result in W register Lecture 21 -PIC Architecture

16. The Banked Option • Have seen that data memory is banked. • Bank 0 – called the “Access Bank” • When assembler is accessing a variable not in the access bank, the BSR register must first be loaded, and then the instruction executed. Lecture 21 -PIC Architecture